1. 1 Reuse Methodology for System-On-Chip Designs 전남대학교 정보통신공학부 교수 김 영 철 Yckim@chonnam.ac.kr

2. 2 Agenda I. Mobile Society Change 1. PC -> Mobile Communication 2. Component -> System II. Design Methodology 1. ASIC Design Flow 2. SoC Design Flow

3. 3 Shift 1: From PC to Communications Centric -> Domain Specific Computing WWW Java Configurable Multi-Standard Info Plug... LAN Broadband Network Services MPEG 4-7 100 Gop/s 5 Gtr/s 10 Watt 100Mb /s WLAN <1 Watt RF 20Gop/s ??

4. 4 Mobile Society 의 환경 변화 PC 시대의 시작 1980 년을 전후로 하여 8-bit/64K Memory PC 시대의 시작 Internet 시대의 시작 PC 통신, E-mail (WS, PC), WWW 시대의 시작 Mobile Phone 시대의 시작 1995 년 전후로 한 Analog Mobile Phone, Digital Phone 시 대의 시작 3 세대 IMT-2000 시대의 시작을 앞두고 있음 Post PC 시대의 시작 다양한 형태의 PDA 를 중심으로 한 Post PC Network Information Appliance 시대를 위한 준비

5. 5 Post-PC Silicon System in 2006 RF / Analog 32 Bit ASPP’s Display Sound Data Bio Actuators 50 GIPS-500GOPS www gps More than IP assembly!! 20 MByte Distributed Memory 200MHz Re-configurable Interconnect FLEXIBILITY - REUSE - IP Embedded Software 1 M gate Re-configurable Computing 1 M Gate Hardwired Logic <1 Volt <1 Watt ENERGY/OP : 100 80nm, 200M+ Transistors Speech Pen Vision Bio Motion Security Sensors

6. 6 Productivity Gap in Hardware Design A growing gap between design complexity and design productivity Source: sematech97

7. 7 Increasing Designer Productivity 7 Areas A : Register-transfer level to layoutB : Low powerC : Libraries D : Analog/mixed-signal designE : Intellectual property reuse F : Hardware/software coverification G : System-level specification

8. 8 ASIC Design - Technology Diffusion

9. 9 ASIC Design - Profit Loss Source: McKinsey

10. 10 Contents Foreword & Preface Introduction System-on-a-Chip Design Process System-Level Design Issues: Rules and Tools Macro Design Process RTL Coding Guidelines Macro Synthesis Guidelines Macro Verification Guideline

11. 11 Contents(2) Developing Hard Macros Macro Deployment: Packaging for Reuse System Integration with Reusable Macro System-Level Verification Issues Data and Project Management Implementing Reuse-Based SoC Designs

12. Foreword Era of multimillion-gate chips 100 M gates and 3 GHz by 2008 (Sematech) 100 gates/day -> 5000 years to complete -> $500 million in today’s dollars How will we get there? Reusable IP(Intellectual Property) is essential Better, Faster, Cheaper devices consumers expect 12

13. Foreword Synopsys and Mentor Graphics joins forces to help make IP reuse a reality -> Reuse Methodology Manual 13

14. 14 Preface Every chapter with additional information - Based on suggestions from readers and on our own experiences - Added some new materials on low-power design for reuse Fundamental theme of any good design discipline: Concept of Locality - Use a fully synchronous design style - Do rigorous, bottom up verification - Plan before doing

15. 15 Chapter 1. Introduction - Silicon technology to build chips consisting of tens of millions of gates - Current design tools and methodologies as inadequate for developing million gate ASICs - Pressure to keep design team size and design schedules constant as design complexities grow - Tools are not providing the productivity gains - The use of predesigned and pre-verified cores: Bridging the gap between available gate-count and designer productivity - Attempt to capture and incrementally improve on current best practices in the industry, and to give a coherent, integrated view of design process

16. 16 1.1 Goals of This document Common set of problems facing everyone – Time-to-market pressure - Quality of results, in performance, area, and power - Increasing chip complexity -> verification more difficult - The development team has different levels and areas of expertise - Hard to reuse previous designs - SoC designs include embedded processor core, and thus significant software component -> leads to additional methodology, process, and organizational challenges.

17. 17 Effective design reuse strategies – How reusable macros fit into an SoC development methodology - How to design reusable soft macros - How to design reusable hard macros - How to integrate soft and hard macros into an SoC design - How to verify timing and functionality in large SoC design

18. 18 Deep submicron techinology presents a whole set of design challenges: – Interconnct delays - Clock and power distribution - place and route of millions of gates - Interconnect issues, floorplanning, and timing design must be addressed early in the design process

19. 19 1.1.1 Assumptions & Definitions Assumptions - HDL design and synthesis - Design for test, including full-scan techniques - Floorplanning, physical synthesis, and place and route Definitions – Macro, Core, Block, IP -> Interchangable terms - Subblock: subcomponent of a macro - Soft macro: deliverable one to integrator as synthesizable RTL code - Hard Macro: deliverable one to the integrator as a GDSII file

20. 20 1.1.3 Virtual Socket Interface Alliance VSIA - An Industry group working to facilitate the adoption of design reuse by setting standards for tool interfaces and design and documentation practices - WGs of VSIA have developed a number of proposals for standards – Virtual Component: VSIA adopted the name VC to specify reusable macro - Firm Macor: VSIA defined an intermediate form between hard and soft macro that can be deliverable in RTL or netlist form with or without detailed placement.

21. 21 1.2 Design for Reuse: The Challenge Principles for design reuse methodology – Creation of every stage of design with the understanding that it will be modified and reused in other projects by other design teams - The use of tools and processes that the design information in a consistent, easy-to-communicate form - The use of tools and processes that make it easy to integrate modules into a design when the original designer is not available

22. 22 1.2.1 Design for Use To be reusable, a design must first be usable: a robust and correct design Good design techniques – Good documentation - Good code - Thorough commenting - Well-designed verification environments and suites - Robust scripts

23. 23 1.2.2 Design for Reuse The macro must be: – Designed to solve a general problem - Designed for use in multiple technologies - Designed for simulation with a variety of simulators - Verified independently of the chip in which it will be used - Verified to a high level of confidence - Fully documented in terms of appropriate applications and restrictions

24. 24 1.2.3 Fundamental Problems The results of experience with problems such as: – The design representation is not appropriate - The design comes with incomplete design informations - Supporting scripts are not available - The full design was never properly archieved - The tools used to develop the design are no longer supported - The tools used to develop the design had poor inter- operability - A hard macro is available, but the simulation model is so slow

25. 25 1.3 Emerging Business Model for Reuse Reuse is not just a technical issue: – Most of the barriers to the adoption of reuse are management and cultural in nature - Look at the business and organization context within which design and design reuse occur - The business models are important for defining the cost-benefit equation that drives when and how reuse occurs in real organization

26. 26 1.3.1 Changing Roles in SoC Design Role in traditional design - Systems groups designed to the RTL level - ASIC group did physical implementation for internal and external customers - Full custom chip design groups designed chips from start to finish Role in SoC Design - Systems house to focus on software and applications aspects of the design - ASIC vendor must do more of the chip integration, manage the IP, and provide simulation and synthesis models to the systems designers

27. 27 1.3.2 Retooling Skills for New Roles Significant retooling of design skills in the industry – System houses are focused on improving software and system architecture skills to differentiate their products - Silicon providers to provide not just silicon, but IP and integration services required to implement very complex chips - Design teams within these silicon providing companies are developing skills and methodologies for integrating IP into large designs

28. 28 1.3.3 Sources of IP for SoC Designs Cell phone chip with advanced features – Design requires a 32-bit processor, a DSP, large amounts of on-chip memory, numerous blocks from previous cell-phone designs, and some new designs for the Internet support blocks - Silicon vendor may provide the processor and DSP - The memory designed by using a memory generator from the silicon vendor - The rest of the blocks from internal sources: Reusing blocks from previous design and developing new blocks

29. 29 1.3.3 Sources of IP for SoC Designs Semiconductor company making automotive chips – Design requires on-chip, 32-bit processor and large amounts of memory plus many blocks from previous generations of designs - The new design integrates multiple chips into one new chip - The processor may be a proprietary processor from another group in the company - Half or more of the other blocks are from other internal groups, who designed the different chips that made up the previous generation chip set

30. 30 1.3.4 Cost Models Drives Reuse Business justification for investing in making designs reusable – Integrating a highly reusable block requires on tenth or less the effort of developing that same block for a single use: 10 times productivity benefit or higher for that part of the design - For not fully designed for reuse, 5 times productivity benefit in using a block that has been designed for reuse, over reusing a block that was not designed for reuse

31. 31 1.3.5 How Much Reuse and When Which blocks should be designed for reuse – 10 times productivity benefit over ten or more chip designs justifies the reuse efforts: Processor, their peripherals, standard interfaces such as PCI and USB - For domain specific blocks such as multi-media or data communication blocks deserve full design-for-reuse if used on several generations of product - Application specific blocks may well not justify the effort to make them reusable - For blocks that will only be used three or four times, such blocks do not warrant full design for reuse, but justify some effort toward reusability