1. VHDL Workshop FSM

2. FSM-Smart Counter Requirements Receives a start signal. When start signal goes high, starts to count from zero: reset value – 0, first clock after start – Out = 1, second clock after start- 2 etc. Counts until a user defined value. When finished, issues a Finish pulse and waits for a new start. Can receive a pause signal active high. In this case, will wait until pause goes down, and then continue

3. FSM-Top Level

4. FSM - Design Idle state Count state Pause state Pause = ‘0’ Pause = ‘1’ Start rising and pause = ‘1’ Start rising and pause = ‘0’ Finished counting

5. FSM – Writing Code Declare states used for FSM FSM divided into two processes: Synchronous – saves next state Asynchronous – decides where to go, control signals We use other processes for help

6. FSM – Declaration and Sync Process Which are FF’s and which are just wires?

7. FSM – Aiding process

8. FSM- Async Process Defaults Assignment at every branch

9. FSM- Async Process-continued

10. FSM- Test Bench

11. FSM – Test Bench - continued

12. FSM- in action

13. FSM - summary Before writing – design Divide into two processes Define states with meaningful names Every signal (wire) must have: An assignment in all possible branches, or Default assignment