1. Design at the Register Transfer Level Algorithmic State Machines 07

2. Register Transfer Level (RTL) Spring'14232 - Logic Design / 07Page 2

3. Verilog … Spring'14232 - Logic Design / 07Page 3

4. 232 - Logic Design / 074 Algorithmic State Machine (ASM)  Our design methodologies do not scale well to real-world problems.  … Spring'14

5. 232 - Logic Design / 075 Algorithmic State Machine (ASM)  Procedure for implementing a problem with a given piece of equipment.  Define ”digital algorithmic solutions” for hardware.  Resembles a conventional flow chart but interpreted differently: ◦ASM describes the sequence as well as the timing of events. ◦Adapted to specify the control sequence and data processing operations. Spring'14

6. 232 - Logic Design / 076 Control and Datapath  A digital system can be split into two components:  Datapath: Manipulates data according to the system requirements.  Control (Unit/Logic): Generates the signals for sequencing the operations in the data processor. Spring'14

7. 232 - Logic Design / 077 State Box Spring'14

8. 232 - Logic Design / 078 Decision Box Spring'14

9. 232 - Logic Design / 079 Conditional Box Spring'14

10. 232 - Logic Design / 0710 ASM Block  One entrance path  Any number of exit paths  Describes the state of the system during one clock-pulse interval.  The operations within the state and the conditional boxes are all executed with a common clock pulse while the system is in state T 1. Spring'14

11. 232 - Logic Design / 0711 ASM chart – State diagram Spring'14

12. 232 - Logic Design / 0712  All the following operations occur simultaneously (in parallel):  A  A+1  If E == 1 then R  0  Depending on the values of E and F, the state is changed to T 2, T 3 or T 4. Spring'14 Timing

13. 232 - Logic Design / 0713 Design Problem  Design a digital system with two flip-flops, E and F, and one 4-bit binary counter, A. The individual flip- flops of A are denoted by A 4, A 3, A 2, and A 1 (where A 4 holding the MSB).  A start signal S initiates system operation by clearing the counter A and the flip-flop F. The counter is then incremented by 1 starting from the next clock pulse and continues to increment until the operations stop. Counter bits A 3 and A 4 determine the sequence of operations: ◦If A 3 == 0, E is cleared to 0 and the count continues. ◦If A 3 == 1, E is set to 1; then if A 4 == 0, the count continues, but if A 4 == 1, F is set to 1 on the next clock pulse and the system stops counting. Spring'14

14. 232 - Logic Design / 0714 Control & Datapath Status Signals Spring'14

15. 232 - Logic Design / 0715 ASM Chart  Design a digital system with two flip- flops, E and F, and one 4-bit binary counter, A. The individual flip-flops of A are denoted by A 4,A 3,A 2, and A 1 (where A 4 holding the MSB).  A start signal S initiates system operation by clearing the counter A and the flip-flop F. The counter is then incremented by 1 starting from the next clock pulse and continues to increment until the operations stop. Counter bits A 3 and A 4 determine the sequence of operations: ◦If A 3 == 0, E is cleared to 0 and the count continues. ◦If A 3 == 1, E is set to 1; then ◦if A 4 == 0, the count continues, ◦but if A 4 == 1, F is set to 1 on the next clock pulse and the system stops counting. Spring'14

16. 232 - Logic Design / 0716 Sequence of Operations CounterFlip-flopsConditionsState A4A3A2A1EF 000010A3=0, A4=0 T1T1 000100 001000 001100 010000A3=1, A4=0 010110 011010 011110 100010A3=0, A4=1 100100 101000 101100 110000 110110T2T2 110111T0T0 L1, L3 L2 L1L2L3 Spring'14

17. 232 - Logic Design / 0717 Sequence of Operations CounterFlip-flopsConditionsStat e A4A3A2A1EF 000010A3=0, A4=0T1T1 000100 001000 001100 010000A3=1, A4=0 010110 011010 011110 100010A3=0, A4=1 100100 101000 101100 110000 110110T2T2 110111T0T0 Spring'14

18. Circuit Design  Datapath ◦ State Boxes ◦ Conditional Boxes  Control Logic ◦ Decision Boxes ◦ State Transitions Spring'14232 - Logic Design / 07Page 18

19. 232 - Logic Design / 0719 The Datapath (3Ed) Spring'14

20. 232 - Logic Design / 0720 The Datapath (4Ed) Spring'14

21. 232 - Logic Design / 0721 State Diagram for Control Spring'14

22. 232 - Logic Design / 0722 State Table Present state symbol Present state InputsNext state Outputs G1G1 G0G0 SA3A3 A4A4 G1G1 G0G0 T0T0 T1T1 T2T2 T0T0 000XX00100 T0T0 001XX01100 T1T1 01X0X01010 T1T1 01X1001010 T1T1 01X1111010 T2T2 11XXX00001 Spring'14

23. 232 - Logic Design / 0723 State Table Present state symbol Present state InputsNext state Outputs G1G1 G0G0 SA3A3 A4A4 G1G1 G0G0 T0T0 T1T1 T2T2 T0T0 000XX00100 T0T0 001XX01100 T1T1 01X0X01010 T1T1 01X1001010 T1T1 01X1111010 T2T2 11XXX00001  D G1 = T 1 A 3 A 4  D G0 = T 0 S + T 1  T 0 = G 0 ’  T 1 = G 1 ’ G 0  T 2 = G 1 Spring'14

24. 232 - Logic Design / 0724 Control Logic Spring'14

25. 232 - Logic Design / 0725 Control Logic Spring'14

26. 232 - Logic Design / 0726 Homeworks please!  All homeworks are due the start of a class. Homeworks submitted after 15 minutes of a class are considered late. ◦ Homeworks submitted late are eligible for a maximum of 80% credit. ◦ Homeworks submitted after one week of their due date are worth at most 60% credit. ◦ Any homeworks not submitted within two weeks of its due date receive no credit.  Academic dishonesty policy: All works (homework, exam, lab preliminaries, etc.) submitted should be fully your own. We have a zero tolerance policy on cheating and plagiarism. Your work will be regularly checked for such misconduct and the following punishment policy will be applied: ◦ Cheating once in a homework will diminish the percentage of your Homework grades to 5%. A second cheating will remain you pointless from Homeworks and can open the way for legal persecution. ◦ If you suspect that someone has copied your homework partially or fully without your consent, tell it now! ◦ At all times you have the right to challenge our decisions on cheating, upon which the case will be processed through the disciplinary channels of the university. However, we would like to remind you that, if found guilty, the legal code of the university proposes a minimum of six month expelsion from the university. Spring'14

27. 232 - Logic Design / 0727 Recall  What’s an ASM?  What are the components?  What’s the design procedure? Spring'14

28. 232 - Logic Design / 0728 Binary Multiplier  How do we do multiplication by hand? In binary? 10111multiplicand 10011multiplier --------------------------------- 10111 10111 00000 00000 10111 110110101product Spring'14

29. 232 - Logic Design / 0729 High-Level View Spring'14

30. 232 - Logic Design / 0730 10111111 1001 ----------------------- 010111 10111 00000 00000 10111 110110101 Datapath for Binary Multiplier  Sum only two binary numbers accumulating the partial sums in Register Q.  Instead of shifting the multiplicand to the left, shift the product to the right  Spring'14

31. 232 - Logic Design / 0731  P: the number of bits in the registers ASM for Binary Multiplier Spring'14

32. 232 - Logic Design / 0732 Initial State Register B Register ARegister Q 10111 C 0000010011 0 101 P =1 Z=0 Spring'14

33. 232 - Logic Design / 0733 Q0 = 1; add B – first partial product Register B Register ARegister QC 10111 10011 0 100 P =1 Z=0 10111 00000 +------ 0 10111 Spring'14 00000

34. 232 - Logic Design / 0734 Shift Right CAQ Register B Register ARegister QC 10111 01011 11001 0 100 P =1 Z=0 Spring'14

35. 232 - Logic Design / 0735 Q0 = 1; add B – second partial product Register B Register ARegister QC 10111 00010 11001 1 011 P =1 Z=0 10111 01011 +------ 1 00010 Spring'14

36. 232 - Logic Design / 0736 Shift right CAQ Register B Register ARegister QC 10111 10001 01100 1 011 P =1 Z=0 Spring'14

37. 232 - Logic Design / 0737 Q0 = 0; Shift right CAQ Register B Register ARegister QC 10111 01000 10110 1 010 P =0=0 Z=0 Spring'14

38. 232 - Logic Design / 0738 Q0 = 0; Shift right CAQ Register B Register ARegister QC 10111 00100 01011 0 001 P =0=0 Z=0 Spring'14

39. 232 - Logic Design / 0739 Q0 = 1; Add B – fifth partial product Register B Register ARegister QC 10111 11011 01011 0 000 P =1=1 Z=0 10111 00100 +------ 0 11011 Spring'14

40. 232 - Logic Design / 0740 Shift right CAQ Register B Register ARegister QC 10111 01101 10101 0 000 P =1 Z=1Z=1 Spring'14

41. 232 - Logic Design / 0741 Trace of the Binary Multiplication Initial conditions : B=10111CAQP Multiplier in Q 00000010011101 Q0 = 1; add B 10111 First partial product 010111100 Shift right CAQ 00101111001 Q0=1; add B 10111 Second partial product 100010011 Shift right CAQ 01000101100 Q0=0; shift right CAQ 00100010110010 Q0=0; shift right CAQ 00010001011001 Q0=1; add B 10111 Fifth partial product 011011000 Shift right CAQ 00110110101 Final product in AQ = 0110110101 Spring'14

42. 232 - Logic Design / 0742 Making the design of the control logic easier Z=0 Spring'14

43. 232 - Logic Design / 0743 Control Logic  Signals to be generated:  T 0 -T 3  L (The Load signal for Register A, that allows the loading the sum into register A.  Spring'14

44. 232 - Logic Design / 0744 Control Circuit implemented with D flip-flops + Decoder Spring'14

45. 232 - Logic Design / 0745 One FF per state  T 0 = T 0 S’ + T 3 Z  T 1 = T 0 S  T 2 = T 1 + T 3 Z’  T 3 = T 2 Z=0 Spring'14

46. 232 - Logic Design / 0746 ASM with Four Control Inputs  Operations are left blank.  We are interested in the design of the control part only.  Four control inputs: w, x, y, z  Four states: T 0 -T 3 needs 2 flip-flops. Spring'14

47. 232 - Logic Design / 0747 Using MUX’es to implement the control logic  Two D flip-flops encode the state.  The state is decoded into state signals T 0 -T 3 by a decoder.  The current state multiplexes the next state.  Challenge: how to set the inputs of the MUX’es? Spring'14

48. 232 - Logic Design / 0748 Multiplexer Inputs Present state Next State Input conditions Multiplexer inputs G 1 G2G2 G1G1 G2G2 MUX1MUX2 0000w’0w 0001w 0110x1x’ 0111 1000y’yz’+yz = y yz 1010yz’ 1011yz 1101y’zy+y’z’ = y+z’ y’z+y’z’ = y’ 1110Y 1111y’z’ Spring'14

49. 232 - Logic Design / 0749 The complete circuit Spring'14

50. 232 - Logic Design / 0750 Count-of-Ones  The system consists of two registers R1 and R2 and a flip-flop E.  The system counts the number of 1’s in the number loaded into R1 and set R2 to that number.  Shift one bit from R1 into E.  If E == 1 then R2++  If Z = = 1 (that is R1 == 0) then stop.  R2 is initialized to all 1’s. Why? Spring'14

51. 232 - Logic Design / 0751 Datapath for Count-of-Ones Spring'14

52. 232 - Logic Design / 0752 Multiplexer Inputs Present state Next State Input conditions Multiplexer inputs G1G2G1G2MUX1MUX2 0000S’0S 0001S 0100ZZ’0 0110 1011None11 1110EE’E 1101 Spring'14

53. 232 - Logic Design / 0753 Control Logic for Count-of-Ones Spring'14

54. 232 - Logic Design / 07Page 54 End of RTL / ASM …

55. 232 - Logic Design / 0755 How to implement the control logic with a PLA? G1G1 G2G2 1 2 3 …. State signals (T 1 -T n ) Output signals Inputs PLA 1 2 3 …. Spring'14

56. 232 - Logic Design / 0756Spring'14

57. 232 - Logic Design / 0757Spring'14