1. 1 CHAPTER 12 REGISTERS AND COUNTERS This chapter in the book includes: Objectives Study Guide 12.1Registers and Register Transfers 12.2Shift Registers 12.3Design of Binary Counters 12.4Counters for Other Sequences 12.5Counter Design Using S-R and J-K Flip- Flops 12.6Derivation of Flip-Flop Input Equations-- Summary Problems

2. 2 Objectives 1.Explain the operation of registers. Understand how to transfer data between registers using tri-state bus 2. Explain the shift register operation, how to build them and analyze operation. Construct a timing diagram for a shift register 3. Explain the operation of binary counters, how to build them using F/F and gates and analyze operation. 4. Given the present state and desired next state of F/F, determine the required F/F/ inputs 5. Given the desired counting sequence for a counter, derive F/F input equations. 6. Explain the procedures used for deriving F/F input equation. 7.Construct a timing diagram for a counter by tracing signals through the circuit.

3. 3 12.1 Registers and Register Transfers 4-Bit D Flip-Flop Registers with Data, Load, Clear, and Clock inputs (Figure 12-1) Grouped together D F/F Using gated clock(a) F/F with clock enable Figure 12-1(b) Symbol for the 4-bit register using bus notation Figure 12-1(c )

4. 4 12.1 Registers and Register Transfers Data Transfer Between Registers

5. 5 12.1 Registers and Register Transfers Logic Diagram for 8-Bit Register with Tri-State Output

6. 6 Data Transfer Using a Tri-State Bus

7. 7 12.1 Registers and Register Transfers How data can be transferred? The operation can be summarized as follows:

8. 8 12.1 Registers and Register Transfers Parallel Adder with Accumulator N-Bit Parallel Adder with Accumulator

9. 9 12.1 Registers and Register Transfers Adder Cell with Multiplexer (Figure 12-6)

10. 10 12-2 Shift Registers Right-Shift Register 0101  1010  1101  0110  1011

11. 11 12-2 Shift Registers 8-Bit Serial-in, Serial-out Shift Register

12. 12 12-2 Shift Registers Typical Timing Diagram for Shift Register

13. 13 12-2 Shift Registers Parallel-in, Parallel-Out Right Shift Register

14. 14 12-2 Shift Registers Shift Register Operation (Table 12-1)

15. 15 12-2 Shift Registers Timing Diagram for Shift Register

16. 16 12-2 Shift Registers The Next-state equations for the F/F are

17. 17 12-2 Shift Registers Shift Register with Inverted Feedback (Figure 12-12)  Johnson Counter A 3-bit shift register 12-12(a)Successive states 12-12(b)

18. 18 12.3 Design of Binary Counters A binary counter using three T F/F to count clock pulses Synchronous Binary Counter (Figure 12-13) Counting sequence CBA: 000  001  010  011  100  101  110  111  000

19. 19 12.3 Design of Binary Counters State Table for Binary Counter (Table 12-2)

20. 20 12.3 Design of Binary Counters Karnaugh Map for Binary Counter (Figure 12-14) TA=1, TB=A, TC=AB

21. 21 12.3 Design of Binary Counters Binary Counter with D Flip-Flops (Figure 12-15)

22. 22 12.3 Design of Binary Counters The D input equations derived from the maps are Karnaugh Maps for D Flip-Flops (Figure 12-16)

23. 23 12.3 Design of Binary Counters State Graph and Table for Up-Down counter (Figure 12-17) When U=1, Up counting When D=1, Down counting

24. 24 12.3 Design of Binary Counters The up-down counter can be implemented using D F/F and gate Binary Up-Down Counter (Figure 12-18)

25. 25 12.3 Design of Binary Counters The corresponding logic equations are When U=0 and D=1, these equations reduce to

26. 26 12.3 Design of Binary Counters Loadable Counter with Count Enable (Figure 12-19) Loadable counter (Figure 12-19(a)) Summarizes the counter operation (Figure 12-19(b))

27. 27 12.3 Design of Binary Counters Circuit for Figure 12-19 (Figure 12-20)

28. 28 12.3 Design of Binary Counters The next-state equations for the counter of Figure 12-20

29. Spring 2004Digital System29 12.5 Counter using J-K Flip-Flop JK Flip-Flop 의 동작 숙지 –Table 12-7 –J K Q + ----------- 0 0 Q 0 1 0 1 0 1 1 1 Q’

30. Spring 2004Digital System30 12.5 Counter using J-K Flip-Flop Same counting sequence as before Complete state table as above Make F/F input maps –from the next state map –J map 의 Q=0 half – same as Q + Q=1 half – all X’s –K map 의 Q=0 half – all X’s Q=1 half – same as (Q + )’ Draw logic diagram

31. Spring 2004Digital System31

32. Spring 2004Digital System32 12.5 Short-Cut method –JK input eq 을 next-state map 으로부터 직접 만드는 방법 ( 즉 J, K map 을 plot 하지 않고 ) –(Note : there’s no A in J A, K A, B in J B, K B, C in J C, K C ) –Q 의 최소화된 J, K input eq 은 Q 에 depend 하지 않음 – J map 의 Q=1 half, K map 의 Q=0 인 half 는 모두 X’s – 변수 Q 를 제거할 수 있음 –Q Q + J K (Table 12-6 c) ----------- 0 0 0 X Q=0 때 J=Q + – J 는 Q 에 independent 0 1 1 X Q + map 의 Q=0 인 half 로부터 J 를 바로 알 수 있음 1 0 X 1 Q=1 때 K=(Q + )’ – K 는 Q 에 independent 1 1 X 0 Q + map 의 Q=1 인 half 로부터 K 를 바로 알 수 있음

33. Spring 2004Digital System33 Short-cut method Summary (p312) Plot the next state (Q+) map Identify Q=0, Q=1 halves of the map Cross out the values of Q on the edge of the map To determine J as a function of remaining variables – loop 1’s on the Q=0 half To determine K as a function of remaining variables – loop 0’s on the Q=1 half Advantages : separate JK maps are unnecessary number of variables is reduced by 1

34. Spring 2004Digital System34 12.6 Counter Design Using D F/F (will be the last lab in this semester) Counting sequence : same as in Fig 12-3 Q + =D  D input map is identical with next-state map D A =A + =B’ D B =B + =A+BC’ D C =C + =AC’+BC’=C’(A+B)

35. 35

36. Spring 2004Digital System36 BCD to Excess-3 Code Converter Cf. p221 How many F/F's are needed? Initially, one of the BCD digits is stored in the F/F's After a pulse is applied to the network, the corresponding excess-3 coded digits should appear in the F/F's

37. Spring 2004Digital System37 Code Converter

38. Spring 2004Digital System38 Shift Registers Shift Register : group of F/F's in which a binary number can be stored SR F/F 을 이용한 4-bit cyclic right-shift register

39. Spring 2004Digital System39 Summary