1. 1 Hardware Tests of Compute Node Carrier Board Hao Xu IHEP, CAS

2. 2 Outline Carrier board design Hardware tests Next steps

3. 3 Carrier Board Design XTCA compliant carrier board 4 AMC connectors, AMC modules for data input and processing FPGA0 for data switching, providing interconnection between AMC modules in the same shelf RTM reservation (xTCA compliant) Clock/trigger/ distributions

4. 4 Block Diagram of Carrier Board

5. 5 Carrier Board Compute Node Ver.3.0- Carrier board 4 AMC connectors FPGA0 for data switching – 2GB DDR2 SDRAM – 512Mb Flash memory – 2 Gbit Ethernet – 16 RocketIOs to backplane RTM connectors

6. Power Supply Card Power supply – -48V to 12V – 5V,3.3V, 2.5V, 1.8V, 1.2V… Hot swap – Carrier board hot swap – 4 AMC modules and RTM hot swap JTAG chain – CPLD -> FPGA0 -> RTM -> AMC1 -> … ->AMC4 – JTAG automatic connecting/bypass UART-USB – 6 UART to USB converters – USB hubs for 6 USB channels 6

7. Power Supply Card (2) Haredware Platform Management Carrier board IPMC – Management is performed through IPMI messaging over an onboard IPMB-L. Each Module has a unique IPMB-L address derived from its geographic address 7

8. Hardware Tests Power supply card tests – Power supply – Hot swap – JTAG chain – USB hub FPGA configuration 8

9. Hot Swap Test Hot swap – Carrier board – AMC modules and RTM Test by setting PS1# and PWR enable to 1/0 – PS1# = 0, AMC is plugged in, MP enabled PWR enable -> PWR on PWR disable -> PWR off – PS1# = 1, MP/PWR disabled 9

10. JTAG Chain JTAG chain – CPLD -> FPGA0 -> RTM -> AMC1 -> … ->AMC4 JTAG automatic connecting/bypass – Default: CPLD and FPGA0 is connected RTM, AMC1-4 are bypassed – Automatic connecting upon requirement from MMC Default state (red line) is OK. 10

11. USB Hub 6 UART to USB converters 2 USB hub chips for 6 USB channels The hardware couldn’t be recognized by PC Hardware problems found 11

12. Next Steps New power supply card product – USB hub chip is changed, only one stage – Board shape is modified, easy to assemble – Layout finished – Will be delivered in this week Function tests of FPGA0 peripheral – DDR2 SDRAM – FLASH memory – Ethernet Joint test with xFP 12

13. 13 Thank you for your attention!