1. Decoder

2. 2 ABC 3:8 dec O0O0 O1O1 O2O2 A B C Enb S2S2 S1S1 S0S0 O3O3 O4O4 O5O5 O6O6 O7O7 EABC O0O0 O1O1 O2O2 O3O3 O4O4 O5O5 O6O6 O7O7 0XXX00000000 100010000000 100101000000 101000100000 101100010000 110000001000 110100000100 111000000010 111100000001 2-to-4, 3-to-8, … n-to-2 n

3. 3 Decoder

4. 4 Design Using Decoder Applications:  Memory Address decoding:

5. 5 Design Using Decoder Applications:  Implementing General Logic  Any combinational circuit can be constructed using decoders and OR gates! F1 = A' B C' D + A' B' C D + A B C D F2 = A B C' D' + A B C F3 = (A' + B' + C' + D') Example: A‘B’C’D’ A ‘B’C’D A‘B’CD’ A‘B’CD A‘BC’D’ A‘BC’D A‘BCD’ A‘ BCD A B’C’D’ A B’C’D A B’CD’ A B’CD A B C’D’ A B C’D A B C D’ A B C D F 1 F 3 F 2 A B C D S2S2 S1S1 S0S0 S3S3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 4:16 dec Enb

6. 6 Active Low Decoder with  Active Low Enable  Active Low Outputs GAB Y0Y0 Y1Y1 Y2Y2 Y3Y3 1XX1111 0000111 0011011 0101101 0111110

7. 7 74x139 dual 2-to-4 decoder

8. 8 74x138 3-8 Decoder

9. 9

10. 10 Using 3-State Buffers  Can use 3-state buffers to share a single line for several devices. Decoder guarantees that no two buffers are on simultaneously. Some decoders have hi-Z outputs.

11. 11 Decoders  Can build a decoder by smaller decoders A B C D S2S2 S1S1 S0S0 S3S3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 4:16 dec Enb 3:8 dec O0O0 O1O1 O2O2 B C D Enb S2S2 S1S1 S0S0 O3O3 O4O4 O5O5 O6O6 O7O7 3:8 dec O0O0 O1O1 O2O2 B C D Enb S2S2 S1S1 S0S0 O3O3 O4O4 O5O5 O6O6 O7O7 A B C D

12. 12 Decoders  How to build a 5-32 decoder by using 4-16 and 2-4 decoders?

13. 13 Decoders Decoder: a more general term  Our focus was on “binary decoders”

14. 14 7-Segment Decoder Seven-segment display:  7 LEDs (light emitting diodes), each one controlled by an input  1 means “on”, 0 means “off”  Display digit “3”?  Set a, b, c, d, g to 1  Set e, f to 0 d a b c e f g

15. 15 7-Segment Decoder C 5 C 0 C 6 C 3 C 4 C 1 C 2 C 0 C 1 C 2 C 3 C 4 C 5 C 6 BCD-to-7-segment control signal decoder ABCD

16. 16 7-Segment Decoder 7-Segment Decoder :  Input is a 4-bit BCD code  4 inputs (A, B, C, D).  Output is a 7-bit code (a,b,c,d,e,f,g) that allows for the decimal equivalent to be displayed. Example:  Input: 0000 BCD  Output: 1111110 (a=b=c=d=e=f=1, g=0) d a b c e f g

17. 17 BCD-to-7Segment Truth Table 11100X001117 X011111 01106 101101101015 011001101004 111100100113 110110100102 011000000011 111111000000 abcdefgABCDDigitabcdefgABCDDigit XXXXXXX1111 XXXXXXX1110 XXXXXXX1101 XXXXXXX1100 XXXXXXX1011 XXXXXXX1010 111X011 10019 111111110008 ?? 1011111 1110000 1110011

18. 18 K-maps a = A + B D + C + B' D' b = A + C' D' + C D + B' c = A + B + C' + D d = B' D' + C D' + B C' D + B' C e = B' D' + C D f = A + C' D' + B D' + B C' g = A + C D' + B C' + B' C AB CD 00011110 00 01 11 10 D B C A 10X1 01X1 11XX 11XX K-map fora AB CD 00011110 00 01 11 10 D B C A 11X1 10X1 11XX 10XX K-map forb AB CD 00011110 00 01 11 10 D B C A 11X1 11X1 11XX 01XX K-map forc AB CD 00011110 00 01 11 10 D B C A 10X1 01X0 10XX 11XX K-map ford AB CD 00011110 00 01 11 10 D B C A 10X1 00X0 00XX 11XX K-map fore AB CD 00011110 00 01 11 10 D B C A 11X1 01X1 00XX 01XX K-map forf AB CD 00011110 00 01 11 10 D B C A 01X1 01X1 10XX 11XX K-map forg

19. Encoder

20. 20 Encoder Encoder:  the inverse operation of a decoder.  Has 2 n input lines and n output lines.  The output lines generate the binary equivalent of the input line whose value is 1. I0 I1 I2 I3 z1 z2 4-2 Binary Encoder

21. 21 Encoder 3:8 decoder O0O0 O1O1 O2O2 A B C S2S2 S1S1 S0S0 O3O3 O4O4 O5O5 O6O6 O7O7 8:3 encoder I0I0 I1I1 I2I2 A B C Z2Z2 Z1Z1 Z0Z0 I3I3 I4I4 I5I5 I6I6 I7I7

22. 22 Encoder Circuit Design Example:  8-3 Binary Encoder A 0 = D 1 + D 3 + D 5 + D 7 A 1 = D 2 + D 3 + D 6 + D 7 A 2 = D 4 + D 5 + D 6 + D 7

23. 23 Encoder Circuit With Enable With Acknowledge

24. 24 Encoder Application Example:  Several peripherals connected to a CPU CPU Enc

25. 25 Application The number of inputs: large  fewer lines

26. 26 Encoder Design Issues  Only one input can be active at any given time.  If two inputs are active simultaneously, the output produces an undefined combination  (for example, if D 3 and D 6 are 1 simultaneously, the output of the encoder will be 111. A 0 = D 1 + D 3 + D 5 + D 7 A 1 = D 2 + D 3 + D 6 + D 7 A 2 = D 4 + D 5 + D 6 + D 7

27. 27 Priority Encoder  Multiple asserted inputs are allowed; one has priority over all others.

28. 28 K-Maps

29. 29 Circuit

30. 30 8-3 Priority Encoder

31. 31 Priority Encoder: Application

32. 32 74x148 Features:  inputs and outputs are active low.  EI_L must be asserted for any of its outputs to be asserted.  GS_L is asserted when the device is enabled and one or more of the request inputs is asserted. (“Group Select” or “Got Something.” )  EO_L is an enable output designed to be connected to the EI_L input of another ’148 that handles lower-priority requests.  It is asserted if EI_L is asserted but no request input is asserted; thus, a lower-priority ’148 may be enabled.

33. 33 74x148 Truth Table

34. 34 Circuit Diagram

35. 35 Datasheets  http://www.techlearner.com/C&D/index.htm  http://users.otenet.gr/~athsam/database.htm http://users.otenet.gr/~athsam/database.htm  Some sample datasheets in the course site.