1. Effect of Load and Store Reuse on Energy Savings for Multimedia Applications 黃國權 洪吉勇 李永恆 曾學文 黃國權 洪吉勇 李永恆 曾學文 Computer Architecture Term Project

2. MotivationMotivation  Most modern microprocessors employ one or two levels caches in order to improve performance. (e.g. L1, L2 cache)  These caches are typically implemented with static RAM cells and often occupy large portion of the chip area and consume a significant amount of power.  Find ways to reduce the power consumption by removal redundancy  Most modern microprocessors employ one or two levels caches in order to improve performance. (e.g. L1, L2 cache)  These caches are typically implemented with static RAM cells and often occupy large portion of the chip area and consume a significant amount of power.  Find ways to reduce the power consumption by removal redundancy

3. Load Reuse  We just focus on the load instruction reuse and evaluate it on the multimedia applications.  Our goal is to reduce both the energy consumed and the execution time  The basic concept is to buffer the results of past load and store instructions and to reuse them.  We just focus on the load instruction reuse and evaluate it on the multimedia applications.  Our goal is to reduce both the energy consumed and the execution time  The basic concept is to buffer the results of past load and store instructions and to reuse them.

4. Experimental Environment  Simulator  SimWattch performance / energy simulator  Benchmark  MediaBench encompass most of the media applications  Simulator  SimWattch performance / energy simulator  Benchmark  MediaBench encompass most of the media applications

5. Reuse Step Reuse checking Buffer refreshing

6. Reuse Checking  Before load access the LSQ, it must check buffer first.

7. Buffer Refreshing  As load write back the result, it must also refresh the reuse buffer.

8. DefinitionDefinition  Original : –Lsq access = load access + store access  Have reuse function : –Lsq access = the load with reusing store instruction + store access  The former load instruction (same or different load) can reduce the times of accessing the LSQ.  Original : –Lsq access = load access + store access  Have reuse function : –Lsq access = the load with reusing store instruction + store access  The former load instruction (same or different load) can reduce the times of accessing the LSQ.

9. MediaBench MPEG -D

10. JPEG –E

11. JPEG –D

12. ADPCM –E

13. ADPCM –D

14. DijkstraDijkstra

15. G721 –E

16. G721 –D

17. EPICEPIC

18. Rijndael -E

19. Rijndael -D

20. FFTssFFTss

21. FFTinvFFTinv

22. SUSANSUSAN

23. Benchmark (1)

24. Benchmark (2)

25. ImageImage

26. MultimediaMultimedia

27. NetworkNetwork

28. TelecommTelecomm

29. SecuritySecurity

30. AutomotiveAutomotive

31. ResultResult  Most benchmarks’ power and access don’t vary with the size of buffer except SUSAN.  Buffer’s size also affect the times of same load reuse and different load reuse. –Same load Different load JPEG-E, JPEG-D,Dijkstra, G721-E, G721-D, –Same load > Different load MPEG-D, EPIC –Same load < Different load SUSAN, FFTss, Rijndael-E, Rijndael-D,  Most benchmarks’ power and access don’t vary with the size of buffer except SUSAN.  Buffer’s size also affect the times of same load reuse and different load reuse. –Same load Different load JPEG-E, JPEG-D,Dijkstra, G721-E, G721-D, –Same load > Different load MPEG-D, EPIC –Same load < Different load SUSAN, FFTss, Rijndael-E, Rijndael-D,

32. ConclusionConclusion  Significant levels of instruction redundancy  Removal of redundancy vary from 1% to 39% by load and store reuse mechanism to achieve energy saving  IPC improvement needs further investigation  Significant levels of instruction redundancy  Removal of redundancy vary from 1% to 39% by load and store reuse mechanism to achieve energy saving  IPC improvement needs further investigation

33. Thank you!! Q & A