1. The ALICE TPC Readout Control Unit 10th Workshop on Electronics for LHC and future Experiments 13 – 17 September 2004, BOSTON, USA Carmen González Gutierrez (CERN – PH/ED) Outline: System overview Readout chain Readout chain Readout Electronics Architecture Readout Electronics Architecture Summary and Conclusions Summary and Conclusions

2. Carmen González Gutiérrez - CERN2 LECC 2004 CERN L. Musa R. Campagnolo C. González Gutiérrez B. Leitao Mota University of Bergen, Norway D.Röhrich K.Ullaland B. Pommersche J. Lien J. Alme Ketil M.Richter University of Oslo, Norway S. Solli Ruprecht-Karls Universität Heidelberg, Germany V. Lindenstruth D. Gottschalk M. Stockmaier V. Kiworra T. Alt T. Krawutschke ZTT Worms, Germany S. Bablock C. Kofler

3. Carmen González Gutiérrez - CERN3 LECC 2004 510 cm E E 114 556 cm System Overview: The ALICE Time Projection Chamber Readout plane segmentation:  18 sector per side  6 readout partition (6 RCU) Large Data Volume :  570132 pads x 1000 samples = 712 Mbytes / event  2 scenarios: Pb – Pb (@ 200 Hz)  142.5 Gbytes / s p – p (@ 1 KHz)  712 Gbytes / s  Data compression (zero suppression) in FEE

4. Carmen González Gutiérrez - CERN4 LECC 2004 Readout Electronics Architecture 1 / 2 PASA ADC Digital Circuit 8 CHIPS x 16 CH / CHIP 8 CHIPS x 16 CH / CHIP CUSTOM IC (CMOS 0.35  m) CUSTOM IC (CMOS 0.25  m ) FEC (Front End Card) - 128 CHANNELS (CLOSE TO THE READOUT PLANE) FEC (Front End Card) - 128 CHANNELS (CLOSE TO THE READOUT PLANE) anode wire pad plane drift region 88  s DETECTOR 570132 PADS gating grid ALTRO RAM A single readout channel is comprised of three units: a charge sensitive preamplifier/shaper (PASA), an 10 bits Analog-to-Digital Converter (ADC) and a digital processing chain with a multi-event-memory 10 bits 40 bits RCU Baseline correction Tail Cancellation Zero supression Amplifier Semi-gauss shaper Multi-event memory Data flow from the detector to the Data Acquisition System (DAQ) DAQ (RORC) DCS TTC

5. Carmen González Gutiérrez - CERN5 LECC 2004 Readout Electronics Architecture 2 / 2 RCU Ethernet ( 1 MB/s ) Detector Data Link ( 200 MB / s ) COUNTING ROOM ALTRO bus ( 200 MB / s ) Local Slow- Control (I 2 C-serial link) ON DETECTOR FEC 128 ch 1 13 2 14 12 25 DCS int. (Ethernet) SIU int. (DDL-SIU) Trigger int. (TTC-RX) FEC 128 ch FEC 128 ch FEC 128 ch FEC 128 ch FEC 128 ch PASA – ADC – DIG. DETECTOR TTC optical Link (Clock, L1 and L2 ) Overall TPC: 4356 Front End Card 216 Readout Control Unit Each of the 36 TPC Sector is served by 6 Readout Subsystems ALTRO Bus Interface Slow Control Interface Data assembler Branch A Branch B RORC (PCI) DCS TTC

6. Carmen González Gutiérrez - CERN6 LECC 2004 Readout Control Unit (RCU) Functions:  Readout related: Configuration of the ALTROs (via the DDL or the DCS) Distribution of the trigger and clock signals (from the TTCrx) FEC data readout and transfer to the DAQ via the DDL by the ALTRO bus (VME-like custom bus)  Slow Control related: Supervision and monitoring:  Configure the power state of the FECs  Temperature, Current and Voltage variations  Read status parameters (L1 and L2 counters …)  Interrupt and error handling by the Local Slow Control bus (I2C-like custom bus) Implementation : The RCU has been implemented as a motherboard with two mezzanine cards: SIU - DDL interface TTC and DCS interface.

7. Carmen González Gutiérrez - CERN7 LECC 2004 Initialization (set up time) The configuration of the electronic (baseline, thresholds, tail cancellation coefficients, etc) can be performed via both DAQ and DCS card Overall configuration data: 7 MByte/RCU  3200 active channels  1000 samples/channel FEC 128 ch PASA ALTRO BC DAQ RCU SIU Interface ALTRO protocol DDL Ethernet DCS ALTRO Bus Interface ALTRO bus Interface Instruction Memory Sequencer TTCrx RORC DCS < 1 s 0.7 s 3 s

8. Carmen González Gutiérrez - CERN8 LECC 2004 Data Readout (run time) FEC 128 ch PASA ALTRO BC L1 custom protocol VME-like 40 data lines 14 ctrl lines 40 bits ALTRO protocol to 32 bit RCU bus protocol ALICE standard DAQ RCU SIU Interface DCS ALTRO Bus Interface TTCrx Data Assembler DDL L2 reject L2 accept RORC ALTRO TTC optical link 3 ms ALTROs memory DETECTOR typical event size

9. Carmen González Gutiérrez - CERN9 LECC 2004 Detector Control System The functional requirements for the DCS interface are the following: Configure power state on all FECs Monitoring:  power and temperature on all FECs using a 4 Channel A/D Converter with an On-Chip Temperature Sensor  different counters (L1, L2, sclk …) Error and Interrupt handling  Temperature or currents over thresholds  Voltages under threshold  Power supply errors  Missed sclk  Protocol errors FEC PASA ALTRO BC ADC Slow Control Interface RCU I 2 C protocol Slow Control Interface Instruction Memory Sequencer Result Memory Interrupt DCS TTCrx Ethernet DAQ custom protocol I 2 C-like 2 serial data lines (sda) serial clock (scl) DCS

10. Carmen González Gutiérrez - CERN10 LECC 2004 RCU Motherboard - Bottom view ALTERA APEX20KE GTL Transceivers Backplane readout connectors

11. Carmen González Gutiérrez - CERN11 LECC 2004 RCU Motherboard - Top view DCS interface DIMM connector Power regulators SIU PMC connectors TEST and DEBUG connectors

12. Carmen González Gutiérrez - CERN12 LECC 2004 TTC and DCS mezzanine card Tasks:  Configuration  RCU  FEC  monitoring / controlling the FEE  configuration/readout of the TTCrx  distributing the L1 and L2 ALTERA Excalibur:  FPGA EP20K100  ARM922T hardwired processor  running Linux stored in a flash memory TTCrx chip (custom) Ethernet bridge

13. Carmen González Gutiérrez - CERN13 LECC 2004 Complete system Assembly FECs Backplane Readout bus

14. Carmen González Gutiérrez - CERN14 LECC 2004 FEE integration with other detector components Configuration for the May 2004 Test-Beam : IROC in Field Cage prototype readout with: 43 FECs ( 5500 channels, ~ 1 % of Alice TPC ) connected to 2 RCUs by 4 branches of ALTRO readout backplanes. 2 DCS boards interfaced to the RCUs and connected to the TTC, 2 SIUs for the DDL

15. Carmen González Gutiérrez - CERN15 LECC 2004 Summary and Conclusions The FEE for the ALICE TPC, which consist of 570132 channels, produces a very large data volume The readout is organized in Front End Cards of 128 channels each 216 Readout Control Units (RCU) are interfaced to 4356 FECs The RCU configures the FECs, distributes the clock and trigger information, reads-out and transfers the data from the detector to the DAQ The full system has been successfully tested with others detector components during the test beam in May 2004 (readout of a 5500 channels IROC in Field Cage prototype)

16. Carmen González Gutiérrez - CERN16 LECC 2004 End of presentation

17. Carmen González Gutiérrez - CERN17 LECC 2004 RCU – FEC Assembly 36 trapezoidal sectors Inner chamber Outer chamber FEC C1 : 18 FECs C6 : 20 FECs C4 : 20 FECs C3 : 18 FECs C2 : 25 FECs FRONT VIEW C5 : 20 FECs Kapton Cable 170 mm 186 mm SIDE VIEW

18. Carmen González Gutiérrez - CERN18 LECC 2004 RCU – FEC Assembly

19. Carmen González Gutiérrez - CERN19 LECC 2004 RCU – FEC Assembly

20. Carmen González Gutiérrez - CERN20 LECC 2004 Final System Overview

21. Carmen González Gutiérrez - CERN21 LECC 2004 The 128 channels Front End Card (FEC) Shaping Amplifiers ALTROs current monitoring & supervision BOARD CONTROLLER voltage regulators power connector readout bus connectors GTL transceivers (back side) 170 mm 190 mm Commercial components  Power regulators  Power connectors  GTL transceivers  4 channel ADC with a temp sensor  1 FPGA (ALTERA ACEX1K)  BC Custom ICs  8 ALTROs per FEC  8 PASA per FEC

22. Carmen González Gutiérrez - CERN22 LECC 2004 DDL - SIU mezzanine card