1. ECE 448 Lab 3 FPGA Design Flow Based on Xilinx ISE and Isim. Using Seven-Segment Displays, Buttons, and Switches.

2. Part 1: Distribution and testing of FPGA boards Part 2: Seven Segment Displays Part 3: User Constraints File Part 4: Buttons and Switches Part 5: Introduction to FPGA Design Flow based on Xilinx ISE Part 6: Introduction to Lab 3 Part 7: Class Exercise Agenda for today

3. Part 1 Distribution and Testing of FPGA Boards

4. Part 2 Seven Segment Displays

6. 4-Digit Seven Segment Display

7. Patterns for Decimal Digits

8. Patterns for Hexadecimal Digits

9. Connection to FPGA Pins

10. Multiplexing Digits

11. Time-Multiplexed Seven Segment Display

12. Counter UP COUNTER UP Counter UP q(k-1..k-2) AN Counter UP SEG(6..0) Cou nter UP rst clk OC SSD_DRIVER OC – One’s Complement

13. Size of the counter 1 ms ≤ 2 k * T CLK ≤ 16 ms f CLK = 100 MHz k = ?

14. Part 3 User Constraint File (UCF)

15. File contains various constraints for Xilinx – Clock Period – Circuit Locations – Pin Locations Every pin in the top-level unit needs to have a pin in the UCF

17. User Constraint File (UCF) - SSD # Seven Segment Displays NET " SEG " LOC = "T17" | IOSTANDARD = "LVCMOS33"; NET " SEG " LOC = "T18" | IOSTANDARD = "LVCMOS33"; NET " SEG " LOC = "U17" | IOSTANDARD = "LVCMOS33 " ; NET " SEG " LOC = "U18" | IOSTANDARD = "LVCMOS33"; NET " SEG " LOC = "M14" | IOSTANDARD = "LVCMOS33"; NET " SEG " LOC = "N14" | IOSTANDARD = "LVCMOS33"; NET " SEG " LOC = "L14" | IOSTANDARD = "LVCMOS33 " ; NET " AN " LOC = "N16" | IOSTANDARD = "LVCMOS33"; NET " AN " LOC = "N15" | IOSTANDARD = "LVCMOS33 " ; NET " AN " LOC = "P18" | IOSTANDARD = "LVCMOS33 " ; NET " AN " LOC = "P17" | IOSTANDARD = "LVCMOS33 " ;

18. User Constraint File (UCF) - LEDs # LEDs NET "LED " LOC = "U16" | IOSTANDARD = "LVCMOS33"; NET "LED " LOC = "V16" | IOSTANDARD = "LVCMOS33"; NET "LED " LOC = "U15" | IOSTANDARD = "LVCMOS33"; NET "LED " LOC = "V15" | IOSTANDARD = "LVCMOS33"; NET "LED " LOC = "M11" | IOSTANDARD = "LVCMOS33"; NET "LED " LOC = "N11" | IOSTANDARD = "LVCMOS33"; NET "LED " LOC = "R11" | IOSTANDARD = "LVCMOS33"; NET "LED " LOC = "T11" | IOSTANDARD = "LVCMOS33";

19. # Buttons NET "CLOCK" LOC = "V10" | IOSTANDARD = "LVCMOS33"; User Constraint File (UCF) CLOCK

20. Part 4 Switches and Buttons

23. User Constraint File (UCF) Switches # Switches NET " SW " LOC = "T10 " | IOSTANDARD = "LVCMOS33 " ; NET " SW " LOC = "T9" | IOSTANDARD = "LVCMOS33"; NET " SW " LOC = "V9" | IOSTANDARD = "LVCMOS33 " ; NET " SW " LOC = "M8 " | IOSTANDARD = "LVCMOS33 " ; NET " SW " LOC = "N8" | IOSTANDARD = "LVCMOS33 " ; NET " SW " LOC = "U8" | IOSTANDARD = "LVCMOS33 " ; NET " SW " LOC = "V8" | IOSTANDARD = "LVCMOS33 " ; NET " SW " LOC = "T5" | IOSTANDARD = "LVCMOS33 " ;

24. Buttons

25. Connection of Buttons to FPGA Pins

26. Debouncing Buttons Bouncing period typically smaller than 10 ms key bounce, t BOUNCE

27. Using DEBOUNCE_RED to Generate Short Pulses (1) RED – Rising Edge Detector

28. Using DEBOUNCE_RED to Generate Short Pulses (2)

29. Debouncer reset input clk output

30. Debouncer

31. k and DD Generics k - width of the counter used to measure the debouncing period DD - debouncing period in clock cycles Values of generics given on the next slide assume that the clock frequency = 100 MHz and thus clock period = 10 ns.

32. k and DD Generics Option 1 (value used for simulation only): DD = 100 assuming bouncing period < 1 μs = 1000 ns condition: DD*10ns = 1000 ns => DD = 100 k=7 because 2^7 > 100 Option 2 (values used for synthesis, implementation, and experimental testing): DD = 1000000 assuming bouncing period = 10 ms condition: DD*10ns = 10ms => DD = 1,000,000 k=21 because 2^21 > 1,000,000

33. Rising Edge Detector - RED Turn a step function into an impulse Allows a step to run a circuit for only one clock cycle Rising Edge Detector

34. clk input output input clk output rising edge detector reset

35. Connection of Buttons to FPGA Pins

36. # Buttons NET "BTNS" LOC = "B8" | IOSTANDARD = "LVCMOS33"; BTNS NET "BTNU" LOC = "A8" | IOSTANDARD = "LVCMOS33"; BTNU NET "BTNL" LOC = "C4" | IOSTANDARD = "LVCMOS33"; BTNL NET "BTND" LOC = "C9" | IOSTANDARD = "LVCMOS33"; BTND NET "BTNR" LOC = "D9" | IOSTANDARD = "LVCMOS33"; BTNR User Constraint File (UCF) Buttons

37. Part 5 Hands-on Session on FPGA Design Flow based on Xilinx ISE and Xilinx ISim

38. Part 6 Introduction to Lab 3 Automated Teller Machine ATM

39. ATM Services 1.Balance Inquiry (BAL) 2.Cash Withdrawal (COUT) 3.Deposit Cash (CIN) 4.Deposit a Check (CHEC) 5.Change PIN (CPIN)

40. Step 1: Entering a PIN Number Default Enter PIN using switches Move to STEP 2

41. Step 2: Choosing an Option BTNU (UP) BTND DOWN BTNR (RIGHT) BTNL LEFT BTNS (Enter) Default

42. Balance Inquiry If “Balance Inquiry” chosen first time For Every other “Balance Inquiry”, display the available balance on 7- segment display To go to Step 2 BTNS (Enter)

43. Cash Withdrawal $10 $20 $100$50 Amount entered using Buttons

44. Cash Withdrawal If amount entered is not a multiple of $20 or greater than $500, display For Insufficient funds, Display If amount entered is a valid amount, it should blink for 5 seconds on the 7-segment display, and the remaining amount is displayed afterwards.

45. Cash Deposit $10 $20 $100$50 Amount entered using Buttons

46. Cash Deposit Total deposit amount is displayed on the seven segment display, starting from 0. Available Balance = Previous Balance + Deposit Amount If available balance is greater than the allowed balance ($1500), display and reset the deposit amount to 0. If amount entered is a valid amount, it should blink for 5 seconds on the 7-segment display, and the Available Balance is displayed afterwards.

47. Check Deposit Check value specified in BCD notation entered using Switches. Available Balance = Previous Balance + Deposit Amount If available balance is greater than the allowed balance ($1500), display and reset the deposit amount to 0. If amount entered is a valid amount, it should blink for 5 seconds on the 7-segment display, and the Available Balance is displayed afterwards.

48. Change PIN New 8-bit PIN entered using Switches If new PIN matches the old PIN, display Otherwise update the new PIN

49. Part 7 Lab Exercise

50. 16-bit Binary Up-Down Counter

51. Counter UP COUNTER UP Counter UP q(k-1..k-2) AN Counter UP SEG(6..0) Cou nter UP rst clk OC SSD_DRIVER OC – One’s Complement