1. EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process Dr. Shiyan Hu Office: EERC 731 Adapted and modified from Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic. EE4271 VLSI Design

2. EE141 © Digital Integrated Circuits 2nd Manufacturing 2 Silicon Wafer Single die Wafer From http://www.amd.com Going up to 12” (30cm)

3. EE141 © Digital Integrated Circuits 2nd Manufacturing 3 N-Well Process

4. EE141 © Digital Integrated Circuits 2nd Manufacturing 4 Dual-Well Process Dual-Well Trench-Isolated CMOS Process Transistors at bottom Wires on the top

5. EE141 © Digital Integrated Circuits 2nd Manufacturing 5 Circuit Under Design

6. EE141 © Digital Integrated Circuits 2nd Manufacturing 6 Its Layout View

7. EE141 © Digital Integrated Circuits 2nd Manufacturing 7 7 VLSI Design and Fabrication Lithography Process Designed Chip Layout Fabricated Chip

8. EE141 © Digital Integrated Circuits 2nd Manufacturing 8 Chip

9. EE141 © Digital Integrated Circuits 2nd Manufacturing 9 9 Lithography System - Simple View Illumination source Mask Objective Lens Aperture Wafer

10. EE141 © Digital Integrated Circuits 2nd Manufacturing 10 Photo-Lithography Process – Full View oxidation optical mask process step photoresist coatingphotoresist removal (ashing) spin, rinse, dry acid etch photoresist stepper exposure development Typical operations in a single photolithographic cycle (from [Fullman]). Part of layout

11. EE141 © Digital Integrated Circuits 2nd Manufacturing 11 An Example: Patterning of SiO2 Si-substrate (a) Silicon base material (b) After oxidation and deposition of negative photoresist (c) Stepper exposure Photoresist SiO 2 UV-light Patterned optical mask Exposed resist SiO 2 Si-substrate SiO 2 2 (d) After development and etching of resist, chemical or plasma etch of SiO 2 (e) After etching (f) Final result after removal of resist Hardened resist Chemical or plasma etch

12. EE141 © Digital Integrated Circuits 2nd Manufacturing Manufacturing Process 12  Part of the layout is put on a mask (level), so we have many masks.  Each mask level corresponds to different actions in the fabrication process  Each mask level contains non-overlapping polygons, but polygons from different masks may overlap subject to max/min distance rules  Minimum geometry (lambda) rule is used. The overlap is defined using lambda rule.

13. EE141 © Digital Integrated Circuits 2nd Manufacturing An Example - I 13

14. EE141 © Digital Integrated Circuits 2nd Manufacturing An Example - II 14

15. EE141 © Digital Integrated Circuits 2nd Manufacturing An Example - III 15

16. EE141 © Digital Integrated Circuits 2nd Manufacturing An Example - IV 16

17. EE141 © Digital Integrated Circuits 2nd Manufacturing An Example - V 17

18. EE141 © Digital Integrated Circuits 2nd Manufacturing An Example - VI 18 Active (diffusion) contact

19. EE141 © Digital Integrated Circuits 2nd Manufacturing An Example - VII 19

20. EE141 © Digital Integrated Circuits 2nd Manufacturing 20 General CMOS Process Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers

21. EE141 © Digital Integrated Circuits 2nd Manufacturing 21 Contact and Via  Contact:  link metal with diffusion (active)  Link metal with gate poly  Via:  Link wire with wire  Overlapping two layers (diffusion, gate poly or metal) and providing a contact hole filled with metal  Substrate Contact and Well Contact:  Link substrate or well to supply voltage

22. EE141 © Digital Integrated Circuits 2nd Manufacturing 22 CMOS Process Walk-Through p + p-epi (a) Base material: p+ substrate with p-epi layer (extended layer) p+ (c) After plasma etch of insulating trenches using the inverse of the active area mask p + p-epi SiO 2 3 SiN 4 (b) After deposition of gate-oxide and sacrificial nitride (acts as a buffer layer)

23. EE141 © Digital Integrated Circuits 2nd Manufacturing 23 CMOS Process Walk-Through SiO (field oxide) 2 (d) After trench filling, CMP planarization, and removal of sacrificial nitride (e) After n-well implants (by adjusting well doping in order to have more donar impurities such as phosphorus) n (f) After p-well implants (by adjusting well doping in order to have more acceptor impurities such as boron) p This implant will only impact the area below the gate oxide but not gate oxide itself

24. EE141 © Digital Integrated Circuits 2nd Manufacturing 24 CMOS Process Walk-Through (g) After polysilicon deposition and etch poly(silicon)

25. EE141 © Digital Integrated Circuits 2nd Manufacturing 25 CMOS Process Walk-Through Interlayer dielectric (between wire and diffusion, between wire and wire)

26. EE141 © Digital Integrated Circuits 2nd Manufacturing 26 CMOS Polysilicon Aluminum

27. EE141 © Digital Integrated Circuits 2nd Manufacturing 27 Metal

28. EE141 © Digital Integrated Circuits 2nd Manufacturing 28 Challenge Illumination source Mask Objective Lens Aperture Wafer 193nm 45nm

29. EE141 © Digital Integrated Circuits 2nd Manufacturing 29 Mask v.s. Printing 0.25µ0.18µ 0.13µ 90-nm65-nm Layout What you design is NOT what you get!

30. EE141 © Digital Integrated Circuits 2nd Manufacturing 30 Motivation  Chip design cannot be fabricated  Gap –Lithography technology: 193nm wavelength –VLSI technology: 45nm features  Lithography induced variations –Impact on timing and power l Even for 180nm technology, variations up to 20x in leakage power and 30% in frequency were reported. Technology node 130nm90nm65nm45nm Gate length (nm) Tolerable variation (nm) 905.3533.75352.5282 Wavelength (nm) 248193193193

31. EE141 © Digital Integrated Circuits 2nd Manufacturing 31 Gap: Lithography Tech. v.s. VLSI Tech. 193nm 28nm, tolerable distortion: 2nm Increasing gap  Printability problem (and thus variations) more severe!

32. EE141 © Digital Integrated Circuits 2nd Manufacturing 32 Design Rules

33. EE141 © Digital Integrated Circuits 2nd Manufacturing 33 Design Rules  Interface between designer and process engineer  Guidelines for constructing process masks  Unit dimension: Minimum line width  scalable design rules: lambda parameter  absolute dimensions (micron rules)

34. EE141 © Digital Integrated Circuits 2nd Manufacturing 34 Lambda Rule  Every distance in layout rules is specified by lambda  Given a process, lambda is set to a specific value.  Process technology is defined using minimum line width. 0.25um technology means minimum line width is 0.25um. Lambda=minimum line width/2.  For a 0.25um process, lambda=0.125um  In practice, scaling is often not linear, e.g., from technology A to B, minimum line width shrink by 0.5, but it does not necessarily mean that minimum poly-diffusion distance also shrinks by 0.5.  Industry usually uses micron rule and lambda rule is used only for prediction/estimation of the impact of technology scaling to a design.

35. EE141 © Digital Integrated Circuits 2nd Manufacturing 35 CMOS Process Layers Layer Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Well (p,n) Active Area (n+,p+) ColorRepresentation Yellow Green Red Blue Magenta Black Select (p+,n+) Green

36. EE141 © Digital Integrated Circuits 2nd Manufacturing 36 Layers in 0.25  m CMOS process

37. EE141 © Digital Integrated Circuits 2nd Manufacturing 37 Intra-Layer Design Rules Metal2 4 3

38. EE141 © Digital Integrated Circuits 2nd Manufacturing 38 Transistor Layout

39. EE141 © Digital Integrated Circuits 2nd Manufacturing 39 Vias and Contacts

40. EE141 © Digital Integrated Circuits 2nd Manufacturing 40 Select Layer

41. EE141 © Digital Integrated Circuits 2nd Manufacturing 41 CMOS Inverter Layout

42. EE141 © Digital Integrated Circuits 2nd Manufacturing 42 Layout Editor

43. EE141 © Digital Integrated Circuits 2nd Manufacturing 43 Design Rule Checker poly_not_fet to all_diff minimum spacing = 0.14 um.

44. EE141 © Digital Integrated Circuits 2nd Manufacturing 44 Some Packages

45. EE141 © Digital Integrated Circuits 2nd Manufacturing 45 Wire Bonding (not printed) Bond wire

46. EE141 © Digital Integrated Circuits 2nd Manufacturing 46 Imprinted Tape-Automated Bonding Disadvantage: Must place I/O pins at the specific locations (i.e., around the boundary on the die).

47. EE141 © Digital Integrated Circuits 2nd Manufacturing 47 Flip-Chip Bonding  Flip-Chip places connection across the chip rather than around boundary.  The bond wire is replaced with solder bump balls directly placed on the die surface  Chip is flipped upside down  Carefully align to package  Heat to melt solder bump balls