1. Highlights from the VTX session Marc Winter & Massimo Caccia R&D reports: – DEPFET (M. Trimpl) – CCD (S. Hillert) – UK-CMOS (J.Velthuis) – Continental-CMOS @Strasbourg (A. Besson) – Continental-CMOS @ DESY (D. Contarato) Impact parameter study (G. Goetz) & discussion

2. p+ n+ rear contact drainbulksource p s y m m e t r y a x i s n+ n internal gate top gateclear n - n+ p+ FET-Transistor integrated in every pixel (first amplification) Electrons are collected in „internal gate“ and modulate the transistor- current + Signal charge removed via clear contact No charge transfer Very limited power consumption (~ 5W for the full VD) - - + + + + - MIP ~1µm 50 µm - - -- -- About the DEPFET pixels

3. Gate Switcher Reset Switcher CURO II I→U ADCs XILINX row wise selection with Switcher System integration of a 64x128 pixel matrix accomplished

4. first results 20 x 25  m 2, double metal matrix SiLAB logo through a 75µm thick tungsten mask 55Fe spectra observed; analysis on the way the steering chip (the SWITCHER) characterized and tested up to 80 MHz (~ 1 mW/channel @ 30 MHz) the read-out chip (the CURO) clocked up to 110 MHz: noise & threshold dispersion according to the specs (~2.8 mW/channel @ 50 MHz) The Next Big Thing: design and produce a 512 x 512 matrix

5. CCD news: the first Column parallel sensor and readout chip have been bump-bonded Signal from a 55 Fe source observed  bump bonding performed by VTT (Finland)  connecting to CCD channels at effective pitch of 20  m possible by staggering of solder bumps 750 x 400 pixels 20  m pitch CPR1

6. More from the LCFI-CCD collaboration: mechanics of the ladder: semi-supported silicon, thinned to epitaxial layer (> 20  m), glued to substrate, e.g. beryllium, carbon fibre composites, ceramics, foams.  BASELINE THICKNESS ~0.1%X 0 /layer early studies on an alternative detector concept to avoid possible problems related to RF-pickup (Image Sensor with In- situ Storage (ISIS)) (NEW PROJECT! JOIN IN!)

7. 4 pixel types, various flavours –Std 3MOS [3T] –4MOS (CDS)[4T] –CPA (charge amp) –FAPS (10 deep pipeline) 3MOS & 4MOS: 64 x 64, 15  m pitch, 8  m epi-layer  MIP signal ~600 e- Row decoder/control 3MOS des. A 3MOS des. B 3MOS des. C 3MOS des. D 3MOS des. E 3MOS des. F 4MOS des. A 4MOS des. B 4MOS des. C 4MOS des. D 4MOS des. E 4MOS des. F CPA des. A CPA des. B CPA des. C CPA des. D FAPS des. A FAPS des. B FAPS des. C FAPS des. D FAPS des. E Columnamplifiers Column decoder/control 5.8 mm Design: R. Turchetta (RAL) UK-CMOS The APS2 chip

8. Tests on the 3MOS and 4MOS structures with a radioactive source: Event displayspectrum - seed pixel - 3x3 cluster - 5x5 cluster Out of 12 substructures 7 feature a S/N > 20 Two structures problems in fabrication Bad pixels: 1-2% Preliminary results on irradiation up to 10 15 p/cm 2 promising

9. Continental CMOS @ Strasbourg The MIMOSA family The new baby is called MIMOSA-9: AMS 0.35  m OPTO-technology  20  m thick epi-layer (the sensitive layer!) cells with 20, 30, 40  m pitch tested at the CERN SPS- 120 GeV  beam: S/N peak ~ 24

10. StandardSelf Bias PITCH (  m) 40203040 Diode size (  m) 3.4 x 4.36 x 63.4 x 4.36 x 63.4 x 4.35 x 53.4 x 4.36 x 6 S/N (Seed)11.020.837.638.132.934.526.227.8 Efficiency90.35±0.498.1±0.1799.87±0.0599.94±0.0399.87±0.0799.81±0.0799.6±0.0997.8±0.23 Summary table of the results: A relevant result since a high efficiency and a fair resolution (~ 5  m level) for a moderate granularity cannot be assumed for granted in CMOS sensors

11. A 1 Mpixel radiation sensor backthinned to 15  m Backthinning the MIMOSA-V (Ires and SUCIMA): First results: Sensitivity to low energy electronsEnergy loss spectrum at the test beam - Backthinned - standard thickness

12. Continental CMOS @ DESY Test beams of the MIMOSA family electron beams up to 6 GeV event rate ~ 5 Hz /cm 2 first tests on the MIMOSA-V chips in August 2004

13. Simulation of the temperature profiles along a module And tests with an evaporative C 3 F 8 coolant (a’ la ATLAS) ongoing