1. V. ReSuperB Workshop, Paris, February 16, 20091 Valerio Re INFN Pavia and University of Bergamo SuperB Workshop Paris, February 15 – 18, 2009 SuperB SVT Layer0: plans on MAPS and pixels with Vertical Integration

2. V. Re2SuperB Workshop, Paris, February 16, 2009 Layer 0 Options Striplets option: mature technology, not so robust against background. Marginal with background rate higher than ~ 5 MHz/cm 2 Moderate R&D needed on module interconnection/mechanics/FE chip (FSSR2) CMOS MAPS option new & challenging technology: can provide the required thickness existing devices are too slow Extensive R&D ongoing (SLIM5-Collaboration) on 3-well devices 50x50um 2 Hybrid Pixel Option: present detectors tend to be too thick. An example: Alice hybrid pixel module ~ 1% X 0 Possible material reduction with the latest technology improvements Viable option for TDR The BaBar SVT technology is adequate for R > 3cm: use design similar to BaBar SVT Layer0 is subject to large background and needs to be extremely thin: > 5 MHz/cm 2, < 0.5%X 0

3. V. Re3SuperB Workshop, Paris, February 16, 2009 Charge-to-Voltage conversion done by the charge preamplifier The collecting electrode (Deep N-Well) can be extended to obtain higher single pixel collected charge (the gain does NOT depend on the sensor capacitance), reducing charge loss to competitive N-wells where PMOSFETs are located Fill factor = DNW/total n-well area ~90% in the prototype test structures PREAMPL SHAPER DISCLATCH Classical optimum signal processing chain for capacitive detector can be implemented at pixel level: Deep N-Well (DNW) sensor concept New approach in CMOS MAPS design compatible with data sparsification architecture to improve the readout speed potential

4. V. Re4SuperB Workshop, Paris, February 16, 2009 Status of Deep N-Well MAPS The first generation of Deep N-Well CMOS MAPS with in-pixel sparsification and time stamping was successfully tested. Sensors with different sparsified readout architectures and pixel pitches were developed for SuperB (large background, equivalent to a continuous beam operation) and for ILC (intertrain readout) in INFN programs. APSEL4D 32x128 matrix. Data Driven, continuously operating sparsified readout Beam test Sep. 2008 50x50 um pitch SDR0 16x16 matrix, Intertrain sparsified readout 25x25 um pitch 90 Sr electrons S/N= 23 Cluster signal (mV) Noise events Average Signal for MIP (MPV) =980e- SLIM5

5. V. Re5SuperB Workshop, Paris, February 16, 2009 Next generation of DNW MAPS has to provide devices that approach actual experiment specifications more closely Several issues have to be addressed to meet SuperB SVT requirements (pixel pitch, detection efficiency): –Binary readout: SVT demands a pixel pitch < 50  m to achieve required hit resolution < 15  m. –Detection efficiency does not meet requirements (~ 99 %) because of competitive n-wells (PMOS) decreasing the fill factor –Readout architecture has to be scaled to a larger matrix size, digital-to-analog interferences should be avoided Two different ways to approach this goal: 1)A gradual performance improvement  better sensor layout, optimize interconnections and pixel cell (remove shaper from APSEL to make room for macropixel lines and to scale to larger dimensions)  SuperB Layer0 test module 2)A technology leap  Vertical integration The way forward

6. V. Re6SuperB Workshop, Paris, February 16, 2009 APSEL5D for a Layer0 module demonstrator Small size prototype module with functionalities and cooling/mechanics close to SuperB specifications New 128x128 (or 320x80) MAPS chip (APSEL5D) –40 mm 2 active area, 40  m x 40  m pixel cells –With respect to APSEL4D, scaling to larger matrix size dictates to remove the shaper stage to make room for additional macropixel private lines –This also makes it possible to reduce the pixel pitch –Inside the pixel cell, sensor layout has to be changed to increase detection efficiency ( → 99%) –A small test chip (APSEL5T) was submitted in January to test pixel cell changes –Optimization of readout architecture strategy is needed for the final chip –Submission of the large matrix APSEL5D in late 2009 in the 130nm CMOS STMicroelectronics technology

7. V. Re7SuperB Workshop, Paris, February 16, 2009 APSEL4D  APSEL5D: analog cell –Pixel cell: 50x50  m 2 –Sensor capacitance: 400 fF –Power dissipation: 30  W –ENC = 60 e rms, threshold dispersion = 60 e (measurements) –Pixel cell: 40x40  m 2 –Sensor capacitance: 270 fF –Power dissipation: 20  W –ENC = 30 e rms, threshold dispersion =25 e (simulations) APSEL4DAPSEL5D CFCF Shaper CDCD VfVf Sensing diode (Deep N-Well) - Preamplifier Discriminator + -V th GmGm C2C2 - iFiF CFCF Discriminator - Sensing diode (Deep N-Well) - + CDCD

8. V. Re8SuperB Workshop, Paris, February 16, 2009 APSEL5T: sensor layout Beam test results of APSEL4D show a ~90% efficiency, which agrees very well with TCAD simulations Optimized cell with satellite N-wells surrounding PMOS competitive N-wells in APSEL5T  Efficiency ~ 99% Metal shielding between analog and digital voltages was improved and made compatible with a large matrix

9. V. Re9SuperB Workshop, Paris, February 16, 2009 A 3D chip is generally referred to as a chip comprised of 2 or more layers of active semiconductor devices that have been thinned, bonded and interconnected to form a “ monolithic ” circuit. Often the layers (sometimes called tiers) are fabricated in different processes. Industry is moving toward 3D to improve circuit performance. –Reduce R, L, C for higher speed –Reduce chip I/O pads –Provide increased functionality –Reduce interconnect power and crosstalk This is a major direction for the semiconductor industry. Vertical integration technologies

10. V. Re10SuperB Workshop, Paris, February 16, 2009 Overcome limitations typically associated to “conventional” and DNW CMOS MAPS: –Reduced pixel pitch –100 % fill factor (few or no PMOS in the sensor layer) –Better S/N vs power dissipation performance (smaller sensor capacitance) –Reduction of digital-to-analog interferences –Increased pixel functionalities (removal of layout constraints allow for an improved readout architecture, analog information,….) –Fully-depleted, high-resistivity substrate: larger signal, fast charge collection, radiation hardness, ….. MAPS and Vertical Integration

11. V. ReSuperB Workshop, Paris, February 16, 200911 Pixel Sensors and Vertical Integration Technologies The very crowded zoo of vertical integration processes can be reduced to two different basic approaches (and technical problems): 1.Interconnection between 2 (or more) CMOS layers, one layer with a MAPS (DNW) device and analog front-end, and the other layer(s) with the digital readout 2.Interconnection between a CMOS readout electronics chip (2D or 3D) and a fully-depleted high resistivity sensor a) with bump bonding (standard, but low pitch may be needed) b) with a vertical integration technique (low material budget, more advanced) –“Pixel systems for thin charged particle trackers based on vertical integration technologies” - VIPIX (INFN Pisa, Pavia, Bologna, Trieste, Trento, Perugia, Roma3, Torino) -Approved and funded INFN program for a 3-year duration

12. 12 V. ReSuperB Workshop, Paris, February 16, 2009 3D vertical integration based on DNW MAPS (conceptual) Use vertical integration technology to interconnect two 130nm CMOS layers NMOS PMOS Standard CMOS Handle for CMOS Deep N-well structure NMOS PMOS Buried N-type layer P-well Standard N-well P-substrate Mostly digital CMOS tier Tier interconnection and vias with industrial technique Analog and sensor CMOS (mostly NMOS) tier

13. V. Re13SuperB Workshop, Paris, February 16, 2009 Cu Tezzaron vertical integration process flow (VIA FIRST): Step 1: Fabricate individual tiers; on all wafers to be stacked: complete transistor fabrication, form super via Fill super via at same time connections are made to transistors Step2: Complete back end of line (BEOL) process by adding Al metal layers and top Cu metal (0.7  m) Step 3: Bond wafer-2 to first wafer-1 Cu-Cu thermo- compression bond multi-tier tier chip; Tezzaron includes standard CMOS process by Chartered Semiconductor, Singapore. All wafers are bulk Wafer-2 Wafer-1 Cu-Cu bond Wafer-n 6  m

14. V. Re14SuperB Workshop, Paris, February 16, 2009 2 nd wafer 1 st wafer 3 rd wafer Tezzaron vertical integration process flow: Step 4: Thin the wafer-2 to about 12 um to expose super via. Add Cu to back of wafer-2 to bond wafer-2 to wafer-3 OR stop stacking now! add metallization on back of wafer-2 for bump bond or wire bond Wafer-2 Wafer-1 Cu for bonding to wafer-3 12um Step 5: Stack wafer-3, thin wafer-3 (course and fine fine grind to 20 um and finish with CMP to expose W filled vias) Add final passivation and metal for bond pads Metal for bonding

15. V. Re15SuperB Workshop, Paris, February 16, 2009 Advantages No handle wafers needed No extra space allotment in BEOL processing for vias Vias are very small Vias can be placed close together Minimal material added with bond process –35% coverage with 1.6 um of Cu gives Xo=0.0056% –No material budget problem associated with wafer bonding. Good models available for Chartered transistors Thinned transistors have been characterized Process supported by commercial tools and vendors Fast assembly Lower cost Via size plays an important role in high density pixel arrays

16. V. Re16SuperB Workshop, Paris, February 16, 2009 3D MPW run A 3D multi project run using Tezzaron/Chartered technology is scheduled at the end of April. There will be only 2 layers of electronics fabricated in the Chartered 130 nm process, using only one set of masks. The wafers will be bonded face to face. Italian groups will join the run in the frame of a 3D-IC Consortium between FNAL, IN2P3 and INFN (http://3dic.fnal.gov)http://3dic.fnal.gov The run will include 3D APSEL structures as a first test of a vertical integration technology for SuperB SVT. The run will also include many other chips by French, U.S. and Italian groups, from MAPS to pixel readout chips (to be bonded to sensors), from which we’ll learn a lot about vertically integrated sensors and electronics

17. V. Re17SuperB Workshop, Paris, February 16, 2009 High resistivity sensors and vertical integration Much better sensor properties with respect to bulk CMOS MAPS (larger and faster signal, radiation hardness,…). Material budget (> 1% X 0 ) and pitch of present HEP hybrid pixel systems is too large for SuperB Vertical integration will help reduce pixel pitch and interconnection material A much better S/N vs. power dissipation vs. speed operating point should be attained with respect to MAPS We plan to use pixel detectors (high resistivity, ~ 50  m pitch) fabricated by FBK-IRST for studying a system based on vertical integration technologies associated to fully depleted sensors

18. V. Re18SuperB Workshop, Paris, February 16, 2009 Bump bonding of 3D CMOS Readout Electronics and high resistivity, fully depleted pixel sensors Standard technique for the interconnection between sensor and electronics; 50  m x 50  m bump bonding pitch appears feasibleStandard technique for the interconnection between sensor and electronics; 50  m x 50  m bump bonding pitch appears feasible A 3D readout integrated circuit may allow for a small pixel pitch (50  m x 50  m) and at the same time for an improved readout architecture (for example removing the 4x4 macropixel structure of the APSEL chips).A 3D readout integrated circuit may allow for a small pixel pitch (50  m x 50  m) and at the same time for an improved readout architecture (for example removing the 4x4 macropixel structure of the APSEL chips). Analog section Digital section detector layer Bump bondin g 1 st layer 2nd layer

19. V. Re19SuperB Workshop, Paris, February 16, 2009 Bump Bonding of small pitch pixels Investigate a bump bonding process compatible with pixelated devices having a 50 micron I/O pitch (technologies are commercially available). 25  m solder bumps on 50 µm pitch, fabricated at RTI SnPb (60/40) Bump Bonds Cu-Sn Bump Bonds 25  m Cu-Sn bump bond, fabricated at RTI

20. V. Re20SuperB Workshop, Paris, February 16, 2009 Readout architecture and vertical integration In APSEL chips, MAPS readout architecture has a macropixel structure to minimize in-pixel logic (and PMOS competitive N-wells). Matrix subdivided in MacroPixel (MP=4x4) with point to point connection to the periphery readout logic: –Register hit MP & store timestamp –Enable MP readout –Receive, sparsify, format data to output bus Data lines in common 2 MP private lines MP 4x4 pixels Periphery readout logic Column enable lines in common Data out bus Vertical integration removes constraints on in-pixel logic and leads to an architecture without macropixels and associated private lines. Readout architecture can be the same for 3D MAPS and for high resistivity pixel sensors.

21. V. Re21SuperB Workshop, Paris, February 16, 2009 Vertical Integration of CMOS Readout Electronics and high resistivity, fully depleted pixel sensors Vertical integration may allow for a considerable reduction of the amount of interconnection material and for a shrinking of the pixel size (40  m x 40  m).Vertical integration may allow for a considerable reduction of the amount of interconnection material and for a shrinking of the pixel size (40  m x 40  m). We plan to verify if the vertical integration process does not degrade a high resistivity sensor.We plan to verify if the vertical integration process does not degrade a high resistivity sensor. Presently, Ziptronix Direct Bonding Interconnect appears the most appealing option for low material budget interconnection.Presently, Ziptronix Direct Bonding Interconnect appears the most appealing option for low material budget interconnection. Analog section Digital section Wafer bonding and electrical interconnection 1 st layer 2nd layer detector layer

22. V. Re22SuperB Workshop, Paris, February 16, 2009 Some 3D bond processes introduce significant material between bonded layers. –Conventional solder bumps or CuSn can pose a problem for low mass fine pitch assemblies IC bonding to a detector will be done by Ziptronix using the Direct Bond Interconnect (DBI) process. 6 –Xo < 0.001% Tezzaron and Ziptronix have formed an alliance. –Good communication between companies for pad metallization for sensor bonding, etc. now exists. Ziptronix is located in North Carolina Orders accepted from international customers Vertical integration between readout chip and fully depleted sensor: Ziptronix

23. V. Re23SuperB Workshop, Paris, February 16, 2009 130 nm 3D Active Pixel Sensors have the potential for a big performance breakthrough targeting SuperB Advanced microelectronic technologies provide exciting opportunities for high performance MAPS and fully depleted pixel sensors A lot of work is needed to qualify these technologies for actual experiments Second run with 3D Tezzaron/Chartered technology and large MAPS matrix and pixel readout chip foreseen in early 2010 Conclusions

24. V. Re24SuperB Workshop, Paris, February 16, 2009 Backup slides

25. V. Re25SuperB Workshop, Paris, February 16, 2009 SuperB SVT Physics goals set severe requirements: –High granularity  small pixel pitch –Low material budget  low mass cooling, thin silicon wafers, small amount of material for support and interconnections –Small distance to interaction point  large background radiation hardness (deep submicron CMOS intrinsically rad-hard) High data rate, Level 1 trigger Data sparsification Mixed-signal chips Full CMOS In MAPS, loss of efficiency due to in-pixel PMOS Digital-to-analog interferences

26. V. Re26SuperB Workshop, Paris, February 16, 2009 Cooling system Vertical integration devices lead to an innovative approach to the cooling problem: –Potentially, requirements are more severe, because vertical integration may substantially increase power per unit surface area available for cooling –Reduction of the impact of the cooling system on the material budget Microchannel cooling –Conservative solution: microchannels in sensor mechanical support –Innovative solution: microchannels in the silicon wafers with front-end electronics (see talk by F. Bosi) Low-Res (electronics) High-Res (sensor) 50  100 um ball-bonded 100 um ~10 um z

27. V. Re27SuperB Workshop, Paris, February 16, 2009 Tezzaron Background Founded in 2000, located in Naperville, Illinois Has fabricated a number of 3D chips for commercial customers Tezzaron uses the “Via First” process Wafers with “vias first” are made at Chartered Semiconductor in Singapore. Wafers are bonded in Singapore by Tezzaron. –Facility can handle up to 1000 wafers/month Bonded wafers are finished by Tezzaron –Bond pads –Bump bond pads Potential Advantages –Lower cost –Faster turn around –One stop shopping!! Process is available to customers from all countries

28. V. Re28SuperB Workshop, Paris, February 16, 2009 Chartered Semiconductor One of the world’s top dedicated semiconductor foundries, located in Singapore, offering an extensive line of CMOS and SOI processes from 0.5 um down to 45 nm. Offers Common Chartered-IBM platform for processes at 90 nm and below. Chartered 0.13 um mixed signal CMOS process was chosen by Tezzaron for 3D integration –Chartered has made nearly 1,000,000 eight inch wafers in the 0.13um process Extension to 300mm wafers and 45nm TSVs underway Chartered 0.13 um process has different layer arrangement and transistor thresholds than IBM process. Commercial tool support for Chartered Semiconductor –DRC – Calibre, Hercules, Diva, Assura –LVS - Calibre, Hercules, Diva, Assura –Simulation – HSPICE. Spectre, ELDO, ADS –Libraries – Synopys, ARM, Virage Logic Chartered Campus

29. V. Re29SuperB Workshop, Paris, February 16, 2009 Chartered 0.13 um Process 8 inch wafers Large reticule – 24 mm x 32 mm Features –Deep N-well –MiM capacitors – 1 fF/um 2 –Reticule size 24 x 32 mm –Single poly –8 levels of metal –Zero Vt (Native NMOS) available –A variety of transistor options with multiple threshold voltages can be used simultaneously Nominal Low voltage High performance Low power Eight inches

30. V. Re30SuperB Workshop, Paris, February 16, 2009 Circuit Performance Circuits tested with full substrate thickness and then after bonding and thinning to 12 um –No change in performance between thinned and bonded devices and unthinned/unbonded devices. Bandgap circuit Sense Amplifier Charge pump –No change in performance between thinned and bonded devices before and after temperature cycling. Transistor measurements on same devices before and after thinning and bonding are shown on the next slide. –No noticeable difference in characteristics except small increase in PMOS speed due to strain in silicon as expected Thinned wafer with test circuits bonded to bottom wafer Bottom wafer Wafer before thinning and bonding

31. TWEPP-0831 Via First Approach Through silicon Via formation is done either before or after CMOS devices (Front End of Line) processing 7 IBM, NEC, Elpida, OKI, Tohoku, DALSA…. Tezzaron, Ziptronix Chartered, TSMC, RPI, IMEC…….. Form vias before transistors Form transistors before vias

32. TWEPP-0832 Via Last Approach Via last approach occurs after wafer fabrication and either before or after wafer bonding 7 Zycube, IZM, Infineon, ASET… Samsung, IBM, MIT LL, RTI, RPI…. Notes: Vias take space away from all metal layers. The assembly process is streamlined if you don’t use a carrier wafer.

33. TWEPP-0833 Bonding Choices Electrical and Mechanical Bonds (MIT LL) (RTI) (Tezzaron) (Ziptronix) Fermilab experience

34. TWEPP-0834 Thinning and Alignment Thinning – –Thinning is done by a combination of grinding, CMP and etching. –Through wafer vias typically have an 8 to 1 aspect ratio for etched vias. Thus, in order to keep the area associated with the vias as small as possible, the wafers should be as thin as possible. Alignment –Alignment of better than 1 um (3 sigma) is now possible on wafer to wafer bonding. 6 inch wafer thinned to 6 um and mounted to 3 mil kapton Photos from MIT LL