2. Digital Receiver and Modulator Architecture for Multi-harmonic RF Finemet Operation 03/11/2015 LLRF15: Digital Receiver and Modulator Architecture for Multi harmonic... 2 J. Molendijk Acknowledgments to: M.E. Angoletta, A. Findlay, M. Haase, M. Jaussi, M. Paoluzzi, J. Sanchez Quesada

3. Outline Operational Experience during CERN PSB Finemet Tests Finemet Milestones Test Setup Cavity Servo loop on Wide-band Finemet Test Setup Resume Proposed Multi Harmonic Scheme Requirements for Operation Receiver / Modulator LO Source Servo Loop in FPGA Receiver and Modulator Clocking Scheme Issues with Sweeping Clock Fixed Frequency Clocked Operation Impact on Receiver Design Outlook & Conclusions 03/11/2015 LLRF15: Digital Receiver and Modulator Architecture for Multi harmonic... 3

4. Operational Experience CERN PSB Finemet Tests Milestones: see also M.E. Angoletta’s talk tomorrow morning on the commissioning 03/11/2015 LLRF15: Digital Receiver and Modulator Architecture for Multi harmonic... 4 2011/2012: Installing first 5 cell Finemet prototype on ring 4 2012: First successful 5 cell beam test using G1 Digital LLRF 2014 LS1: Installation 5 additional Finemet cells on ring 4 2014: Installation and commissioning of G2 Digital LLRF CERN PSB rings R1 to R4 + extra LLRF R0 multiplexed on R4 for Finemet tests November 2014: First successful 10 cell beam test using G2 digital LLRF 2015: Continued machine developments with Finemet system September 2015: 2 nd Finemet review, CERN PSB 100% Finemet now on roadmap. 10 Cell Finemet Cavity CERN PSB R4 section 6L1

5. Operational Experience CERN PSB Finemet Tests Test Setup 03/11/2015 LLRF15: Digital Receiver and Modulator Architecture for Multi harmonic... 5 2015 run: ferrite & Finemet ® -based HLRF systems characteristics & usage. DLLRF R = 25 m C04 C16 C02 Finemet (10 cells) < 2 µs electrical delay between LLRF & Finemet (round trip). C02 C04 C16

6. Operational Experience CERN PSB Finemet Tests Test Setup 03/11/2015 LLRF15: Digital Receiver and Modulator Architecture for Multi harmonic... 6 Ring 4 Ring 3 Ring 2Ring 1 Ring 0 Finemet Servo Loops

7. Operational Experience CERN PSB Finemet Tests Cavity Servo loop on Wide-band Finemet 03/11/2015 LLRF15: Digital Receiver and Modulator Architecture for Multi harmonic... 7 To DSP D 3 / 4 Harmonics 4 CH ADC FMC

8. Operational Experience CERN PSB Finemet Tests Cavity Servo loop on Wide-band Finemet 03/11/2015 LLRF15: Digital Receiver and Modulator Architecture for Multi harmonic... 8 From DSP D 3 / 4 Harmonics 4CH DAC FMC

9. Operational Experience CERN PSB Finemet Tests Cavity Servo loop on Wide-band Finemet 03/11/2015 LLRF15: Digital Receiver and Modulator Architecture for Multi harmonic... 9 Configuration of Finemet Test D-LLRF: One independent servo-loop per harmonic (to be controlled) With separate ADC (hardware Demodulator) & DAC (Modulator) Field regulation uses DSP with T s = 10 µs One DSP can deal with 4 harmonics External loop delay (cables, amplifiers, cavities) about 2 µs Reduced regulation bandwidth ~15 kHz max. due to DSP dominated loop delay

10. Operational Experience CERN PSB Finemet Tests Cavity Servo loop on Wide-band Finemet 03/11/2015 LLRF15: Digital Receiver and Modulator Architecture for Multi harmonic... 10 Typical Loop filter Leaky Integrator @ 2 kHz (~synchrotron side-band) only 14dB (5x) error reduction 60 Magnitude dB 40 20 0 Open Loop with DSP delay Phase Degree 0 -45 -90 -135 -180 Closed Loop with DSP delay 0 -2 -4 -6 -8 0 -45 -90 -135 -180 101  rad/s 10110 5 10 4 10 3 10 2 10 3 10 4 10 5  rad/s Magnitude dB Phase Degree 2 kHz

11. Operational Experience CERN PSB Finemet Tests Test Setup Resume 03/11/2015 LLRF15: Digital Receiver and Modulator Architecture for Multi harmonic... 11 Excellent results with high intensity beam, controlling only 4 harmonics Harmonics 1,2,3 and 5 Typically one driven and others set to 0V Limited regulation bandwidth (DSP bound) Moderate synchrotron side-band impedance reduction, excellent on the carrier Excessive use of hardware and DSP resources Need a complete DSP FMC Carrier for every 4 additional harmonics At least 8 harmonics would be desired Beam Segment

12. Proposed Multi Harmonic Scheme Requirements for Operation 03/11/2015 LLRF15: Digital Receiver and Modulator Architecture for Multi harmonic... 12 A single DSP FMC Carrier for all (8) needed harmonics Receivers only use a single ADC Antenna Vector sum must at all times fit in the ADC dynamic range, was already the case with the previous method! Modulators only use a single DAC Sum of all harmonics must at all times fit in the DAC dynamic range, unavoidable due to power chain limitations Economic creation of all LO harmonics needed for RX and TX Using one pipe-lined CORDIC per LO harmonic is unacceptable Direct cavity servo loop implementation in the FMC FPGA Increase the regulation bandwidth by a factor 5 (electronics delay <=1 µs) No more DSP run-time limitations with // processing

13. Proposed Multi Harmonic Scheme Receiver 03/11/2015 LLRF15: Digital Receiver and Modulator Architecture for Multi harmonic... 13 Single ADC multi-channel Receiver Simply one ADC to several demodulators Each demodulator converts one harmonic to base-band Each harmonic needs own LO All need suitable LPFs to reject other mixing products No more need for analogue Antenna signal distributor

14. Proposed Multi Harmonic Scheme Modulator 03/11/2015 LLRF15: Digital Receiver and Modulator Architecture for Multi harmonic... 14 Single DAC multi-channel Modulator All digitally modulated harmonics are added digitally before the DAC Each harmonic needs own LO Eliminates the need for the analogue RF combiner

15. Proposed Multi Harmonic Scheme LO Source 03/11/2015 LLRF15: Digital Receiver and Modulator Architecture for Multi harmonic... 15 Classical LO (Complex DDS) Phase Accumulator  (t) =  [rad/s] cos(  t), sin(  t) Phase Accumulator: Simple (FTW) integrator Low resource cost Supports FTW ≠ 2 N Angle to cos, sin convertor: Either pipe-line CORDIC (Logic intense, Universal) Lookup tables (memory intense, can be reduced by folding tricks) Example: 32 bit NCO Both solutions cannot be concurrently used: We need one per generated harmonic!

16. Proposed Multi Harmonic Scheme LO Source 03/11/2015 LLRF15: Digital Receiver and Modulator Architecture for Multi harmonic... 16 Economic Multi harmonic LO Source (Complex DDS) Start with one single pipe-lined CORDIC based Complex LO Generate 1 th harmonic: Complex multiply with itself to get the 2 nd harmonic: Generally to get the n th harmonic: Maximal achievable frequency limited to the Nyquist frequency (f s /2).

17. Proposed Multi Harmonic Scheme LO Source 03/11/2015 LLRF15: Digital Receiver and Modulator Architecture for Multi harmonic... 17 Economic Multi harmonic LO Source in Practice Complex Multiplication Complex Multiply XILINX VIRTEX 5 Need 4 DSP48E (XILINX VIRTEX 5) per additional harmonic The XC5VSX95T (FMC FPGA) has 640 DSP48Es

18. Proposed Multi Harmonic Scheme LO Source 03/11/2015 LLRF15: Digital Receiver and Modulator Architecture for Multi harmonic... 18 Economic Multi harmonic LO Source in Practice Potential Issues and counter measures: Small gain errors will accumulate! Use limiting adders / multipliers to keep cos & sin signals btw. +/-1 Make vector magnitide slightly > 1 (Ae j  t with A = 1 + δ ) Without measures output phase of different harmonics will slip (FF in output) Add pipe-line registers to maintain phasing

19. Proposed Multi Harmonic Scheme Servo Loop in (FMC) FPGA 03/11/2015 LLRF15: Digital Receiver and Modulator Architecture for Multi harmonic... 19 One servo loop for each harmonic Selectable setpoint from a function channel or a constant Register assignable function channel Loop Phasing Individual Phase Offset setting Individual Delay Compensation settings Updated once per DSP cycle Needs an additional complex multiplier (implement vector rotation) Shared pipe-lined CORDIC sequentially used by all harmonics Cos and sin conversion from multiplexed sum of Offset and delay compensation

20. Proposed Multi Harmonic Scheme Servo Loop in (FMC) FPGA 03/11/2015 LLRF15: Digital Receiver and Modulator Architecture for Multi harmonic... 20

21. Receiver an Modulator Clocking Scheme Issues with Sweeping Clock 03/11/2015 LLRF15: Digital Receiver and Modulator Architecture for Multi harmonic... 21

22. Receiver an Modulator Clocking Scheme Impact on Receiver Design 03/11/2015 LLRF15: Digital Receiver and Modulator Architecture for Multi harmonic... 22 What if we operate the clocks at a fixed rate? Advantages ADC can be clocked at a much more favourable constant frequency (best noise performance) Eliminates ADC non linearity effects (harmonics) from folding back into the band of interest No more need to change clock harmonic as the dynamic tuning is done in all LOs, able to create any frequency Disadvantages Must tune all LOs synchronously otherwise fatal de-phasing Receiver CIC filters no longer synchronous with f rev and will not benefit from the nulls to suppress unwanted mixing products

23. Receiver an Modulator Clocking Scheme Impact on Receiver Design 03/11/2015 LLRF15: Digital Receiver and Modulator Architecture for Multi harmonic... 23 Issues fixed clock rate operation?: Fatal de-phasing? Distribute Fixed MDDS Clock Each DSP update Generate TAG through MDDS interface to synchronise LO updates with DSP tuning data (reliable at fixed frequency clock) Unwanted Mixing products suppression? Better filter required like decimating CIC cascade (fairly economic but there is no free lunch)

24. Conclusion and Outlook 03/11/2015 LLRF15: Digital Receiver and Modulator Architecture for Multi harmonic... 24 Multi harmonic Servo loops are essential for future CERN PSB 100% Finemet operation Moving the servo loops from the DSP to the FPGA will improve the regulation bandwidth by at least a factor 5 With the proposed optimisations it seems feasible to fit such a system (>= 8 harmonics) in the available FPGA resources Such a system will simplify the external and LLRF hardware to the minimum For the upcoming (2016) ELENA (decelerator) RF system, spanning a very large frequency range (decade), it will make life much easier with a fixed frequency clock scheme going Clocking scheme and Servo loops to be validated 2016 to pave the road for the CERN PSB to 100% Finemet conversion (scheduled for LS2 2019)

25. Thank you for your Attention 03/11/2015 LLRF15: Digital Receiver and Modulator Architecture for Multi harmonic... 25

26. Backup Slides 03/11/2015 LLRF15: Digital Receiver and Modulator Architecture for Multi harmonic... 26

27. Operational Experience CERN PSB Finemet Tests Test Setup 03/11/2015 LLRF15: Digital Receiver and Modulator Architecture for Multi harmonic... 27 1 2 3 5 Harmonic 1 2 3 5 DSP D DSP E Not commissioned DSP E Not commissioned D LLRF

28. Receiver Principle 03/11/2015 LLRF15: Digital Receiver and Modulator Architecture for Multi harmonic... 28 The CIC low-pass filtered mixing product in green Trajectory of Δ  I Q

29. Modulator Principle 03/11/2015 LLRF15: Digital Receiver and Modulator Architecture for Multi harmonic... 29 If we define the DSP signal as: then: and

30. Pipe-line CORDIC 03/11/2015 LLRF15: Digital Receiver and Modulator Architecture for Multi harmonic... 30 Needs lots of logic resources Number of stages further dependent of target precision (ex: 14 for 16 bit)

31. Fixed Frequency Clock Choice 03/11/2015 LLRF15: Digital Receiver and Modulator Architecture for Multi harmonic... 31 Starting from the LO DDS equation and the Maximum ADC clock frequency: We then get: As a compromise select integer M = 35: