1. Intel 8259A PIC EEE 365 [FALL 2014] LECTURE 21 ATANU K SAHA BRAC UNIVERSITY

2. EEE 365 : MICROPROCESSOR ATANU K SAHA 2 PIC  Priority Interrupt controller  In designing an embedded system, we may need interrupts from different sources. Each of these interrupt applications requires a separate interrupt input. If we are working with an 8086, we have a problem here because the 8086 has only two interrupt inputs. If we save NMI for power failure problem, this leaves only one interrupt input for all the other applications.  For applications where we have interrupts from multiple sources, we use priority interrupt controller (PIC) to ‘funnel’ the interrupt signals into a single interrupt input on the processor. Need for a PIC BRAC UNIVERSITY

3. EEE 365 : MICROPROCESSOR ATANU K SAHA 3  If 8086 IF is set and the INTR input receives a high signal, then 8086 will send out two interrupt acknowledge pulses from its INTA pin to the INTA pin of an 8259A PIC. The INTA pulses tell the 8259A to send the desired interrupt type to the 8086 on the data bus.  Multiply the interrupt type it receives from 8259A by 4 to produce an address in the interrupt vector table.  Then 8086 will execute the corresponding ISR. Communication between INTR and PIC BRAC UNIVERSITY Type vector from 8259A Float ALE from 8086 AD0-AD15 Fig: 8086 interrupt-acknowledge machine cycles

4. EEE 365 : MICROPROCESSOR ATANU K SAHA 4 8259A Internal Block Diagram BRAC UNIVERSITY

5. EEE 365 : MICROPROCESSOR ATANU K SAHA 5  IMR (Interrupt Mask Register) is used to disable (mask) or enable (unmask) individual interrupt inputs. Each bit in this register corresponds to the interrupt input with the same number. To unmask an input, a zero is to be sent in the corresponding bit position and to mask an input, an one is to be sent in the corresponding bit position.  IRR (Interrupt Request Register) keeps track of which interrupt inputs are asking for service. If an input has an interrupt signal on it, then the corresponding bit in the IRR will be sent.  An interrupt input signal must remain ‘HIGH’ on an IR input until the falling edge of the first INTA pulse.  ISR (Interrupt Service Register) keeps track of which interrupt inputs are currently being serviced. For each input that is currently being serviced, the corresponding bit will be set in the ISR.  The priority resolver acts as a ’judge’ that determines if and when an interrupt request on one of the IR inputs get serviced. How 8259A Works BRAC UNIVERSITY

6. EEE 365 : MICROPROCESSOR ATANU K SAHA 6 Program Flow BRAC UNIVERSITY STI MAINLINE INITIALIZE 8259A UNMASK IR2, IR4 STI IR4 PROCEDURE IR2 PROCEDURE EOI COMMAND IRET EOI COMMAND IRET 8259A and 8086 program flow for IR4 interrupt followed by IR2 interrupt (Response with INTR enabled in IR4 procedure)

7. EEE 365 : MICROPROCESSOR ATANU K SAHA 7 Program Flow BRAC UNIVERSITY 8259A and 8086 program flow for IR4 interrupt followed by IR2 interrupt (Response with INTR disabled in IR4 procedure) MAINLINE INITIALIZE 8259A UNMASK IR2, IR4 STI IR4 PROCEDURE IR2 PROCEDURE EOI COMMAND IRET EOI COMMAND IRET

8. EEE 365 : MICROPROCESSOR ATANU K SAHA 8 8259A Cascading BRAC UNIVERSITY Each 8259A can take interrupts from eight sources. If 8086 need more interrupt to handle then we need to connect multiple 8259A PIC in cascaded (Master-Slave) form.  If a slave receives an interrupt on one of its IR input, it will send an INT signal to the IR input of the master if That IR is unmasked on the slave That IR is a higher priority than any other IR being serviced in the slave  If that input is unmasked and of highest priority at that time master will send an INT signal to 8086  8086 will send two INTA pulses to both the master and slave  The slave ignores the first acknowledgement pulse, but the master then outputs a 3-bit slave identification number in CAS pins which enables the specific slave  When the slave receives the second INTA pulse from 8086, the slave will send the interrupt type number to the 8086 on the lower 8 data bus lines.

9. EEE 365 : MICROPROCESSOR ATANU K SAHA 9 8259A System Connection BRAC UNIVERSITY

10. EEE 365 : MICROPROCESSOR ATANU K SAHA 10 8259A Initialization and sequence BRAC UNIVERSITY 1.Initialization Command Words (ICWs): To determine the basic operating mode of the PIC. ICWs must be completed before continuing on to the second type of command word. 2.Operation Command Words (OCWs): Can be written into the PIC anytime after the ICWs are written. The OCWs customize the priority features and give the user the ability to write/read various registers. The OCWs also tell the PIC to operate in various interrupt modes. ICW1 ICW2 ICW3 ICW4 Ready to accept INTR In cascade mode Is ICW4 needed ICW1 and ICW2 are compulsory command words in the initialization sequences ICW3 and ICW4 are optional ICW3 is read only when more than one 8259 used in the system (SNGL bin in ICW1 is 0)

11. EEE 365 : MICROPROCESSOR ATANU K SAHA 11 8259A Initialization BRAC UNIVERSITY A0D7D6D5D4D3D2D1D0 0A7A6A51LTIMADISNGLIC4 D0IC4ICW4 required?0  No 1  Yes D1SNGLSingle or Cascaded0  Cascaded 1  Single D2ADIAddress interval0  4 bytes (8086) 1  8 bytes (8085) D3LTIMLevel triggered or edge triggered interrupt 0  Edge triggered 1  Level triggered D4-D7A7-A5 of interrupt vector addressNot for 8086 ICW1

12. EEE 365 : MICROPROCESSOR ATANU K SAHA 12 8259A Initialization BRAC UNIVERSITY A0D7D6D5D4D3D2D1D0 1 A15/T7A14/T6A13/T5A12/T4A11/T3A10A9IA8 ICW2 T7-T3 : Interrupt vector address for 8086/8088 A15-A8 : Interrupt vector address for MCS-80/85 T  Type Each 8259A has 8 interrupt input. So each 8259A can handle 8 types of interrupt. 8086 can handle 256 types interrupt (need 8 bits to define type) If T 7 T 6 T 5 T 4 T 3 = 0 0 1 1 1, then it means IR0 pin of 8259A corresponds to Type 56 (0 0 1 1 1 0 0 0) IR0Type 56 (00111000) IR1Type 57 (00111001) IR2Type 58 (00111010) IR3Type 59 (00111011) IR4Type 60 (00111100) IR5Type 61 (00111101) IR6Type 62 (00111110) IR7Type 63 (00111111)

13. EEE 365 : MICROPROCESSOR ATANU K SAHA 13 8259A Initialization BRAC UNIVERSITY A0ModeD7D6D5D4D3D2D1D0 1 MasterS7S6S5S4S3S2S1S0 Slave00000ID3ID2ID1 Master mode1  Slave is present on that IR input 0  Direct interrupt on that IR input Slave modeID3-ID2-ID1: Slave ID number Slave ID is equal to the corresponding Master input Slave 4 on IR4 has ICW3 = 04 H (00000100) ICW3 For SNGL mode ICW3 is read only. We don’t have to send ICW3

14. EEE 365 : MICROPROCESSOR ATANU K SAHA 14 8259A Initialization BRAC UNIVERSITY A0D7D6D5D4D3D2D1D0 1000SFNMBUFM/SAEOIμPM D4SFNMSpecial fully nested mode0  No 1  Yes D3BUFBuffered mode0  No 1  Yes D2M/SMaster/Slave0  Slave 1  Master D1AEOIAuto end of interrupt0  No 1  Yes D0μPMμProcessor type0  MCS-80/85 1  8086/8088 ICW4

15. EEE 365 : MICROPROCESSOR ATANU K SAHA 15 8259A Initialization BRAC UNIVERSITY A0D7D6D5D4D3D2D1D0 1M7M6M5M4M3M2M1M0 OCW1 Mn  0 : IRn unmasked (enable) Mn  1 : IRn masked (disable)

16. EEE 365 : MICROPROCESSOR ATANU K SAHA 16 8259A Initialization BRAC UNIVERSITY A0D7D6D5D4D3D2D1D0 0RSLEOI00L2L1L0 OCW2 RSLEOIAction End of interrupt (EOI) 001Non specific EOI (L 2 L 1 L 0 = 000) 011Specific EOI (Interrupt to clear given by L 2 L 1 L 0 ) Auto rotation of priorities (L 2 L 1 L 0 =000) 101Rotate priorities on non-specific EOI 100Rotate priorities in auto EOI mode set 000Rotate priorities in auto EOI mode clear Specific rotation of priorities (Lowest priority ISR =L 2 L 1 L 0 ) 111Rotate priorities on specific EOI (reset current ISR bit) 110Set priority (does not reset current ISR bit) 010No operation We have to send OCW2 within the interrupt procedure to define end of interrupt

17. EEE 365 : MICROPROCESSOR ATANU K SAHA 17 8259A Initialization BRAC UNIVERSITY A0D7D6D5D4D3D2D1D0 0xESMMSMM01PRRRIS OCW3 RRRISAction 0XNo action 10Read IR register on next RD pulse 11Read ISR register on the next RD pulse ESMMSMMAction 0XNo action 10Reset special mask 11Set special mask P : 1  Poll command, 0  No poll command

18. EEE 365 : MICROPROCESSOR ATANU K SAHA 18 8259A Initialization Example BRAC UNIVERSITY Example1: Write a program that will initialize an 8259A for the following purpose 1.Need ICW4, Edge sensitive, Single 8259A 2.IR0 will handle type 64 interrupt 3.System is 8086 based 4.IR0 and IR1 is unmasked 5.8259A resides FF00 H as a port Solution: ICW1  00010011 ICW2  01000000 ICW3  read only ICW4  00000001 OCW1  11111100 ; assembly code CLI MOVAL,00010011B MOVDX,FF00H OUTDX,AL;ICW1 MOVAL,01000000B MOVDX,FF02H OUTDX,AL;ICW2 MOVAL,00000001B OUTDX,AL;ICW4 MOVAL,11111100B OUTDX,AL ;OCW1 STI

19. EEE 365 : MICROPROCESSOR ATANU K SAHA 19 8259A Initialization Example BRAC UNIVERSITY Example2: Analyzing the following connection determine the operation and initialize the 8259A for an 8086 system to take type 64 interrupt Solution: 1.Need ICW4, Edge sensitive, Single 8259A 2.IR0 will handle type 64 interrupt 3.System is 8086 based 4.IR0 is unmasked 5.8259A resides FF00 H as a port So, ICW1  00010011 ICW2  01000000 ICW3  read only ICW4  00000001 OCW1  11111110