1. DEPARTMENT OF ELECTRONICS ENGINEERING
v-semester
MICROPROCESSOR & MICROCONTROLLER
CHAPTER NO.3
8086 & Peripheral Interfacing II

2. CHAPTER 3:- SYLLABUS .
Topic 1: Programmable interval timer/counter 8254 1
Topic 2: Architecture, working modes, interfacing 8259 PIC 2
Topic 3: Organization, control words, interfacing, cascading of
8259’s 3
Topic 4: Serial communication, Classification & transmission formats, USART 8251, Pins & block diagram 4
Topic 5: Interfacing with 8086 & programming 5
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3. CHAPTER-3 SPECIFIC Objective / course outcome
The student will be able to:
Learn Programmable interval timer/counter 8254 1
Understand Organization, control words, interfacing, cascading of 8259’s 2
Learn Serial communication, Classification & transmission formats of USART 8251 3
Understand Architecture, working modes, interfacing 8259 PIC 4
Interface I/O devices to 8086 & write program for it. 5
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4. Features LECTURE 24:- 8254/8253 Software-Programmable Timer/Counter
8254 is very versatile and can be used in many applications
There are several modes of operation for different applications.
Intel 8253 and 8254 are almost pin-to-pin compatible except
The maximum input clock frequency for 8253 and 8254 is 2.6 MHz and 8 MHz, respectively. (10MHz for ) 4
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5. 8254/8253 Software-Programmable Timer/Counter
LECTURE 24:-
8254/8253 Software-Programmable Timer/Counter
Continue….
8254 has a read-back feature which allows you to latch the count in all the counters and the status of the counter at any point does not have this feature.
8254 contains three 16-bit counters. The counter can be programmed to load the initial count, start and stop the count.
8254 has an 8-bit interface to data bus, and two address input A0 and A1 to address each of the three counters. 5
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6. 8254 Software-Programmable Timer/Counter
LECTURE 24:-
8254 Software-Programmable Timer/Counter
D7-D0: System data bus
CLK0: Clock for counter 0
Gate0: Gate for counter 0
CLK1: Clock for counter 1
Gate1: Gate for counter 1
CLK2: Clock for counter 2
Gate2: Gate for counter 2
A1-A0: Address select
00: Counter 0
01: Counter 1
10: Counter 2
11: Control Register
Vcc: Power (+5V)
Ground:
RD: Read enable
WR: Write enable
CS: Chip select signal
OUT0: Output of counter0
OUT1: Output of counter1
OUT2: Output of counter2
Figure 3.1:-Pin Diagram of 8254 6
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7. LECTURE 24:-
THANK YOU
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8. 8254 Software-Programmable Timer/Counter
LECTURE 25:-
8254 Software-Programmable Timer/Counter 8
Figure 3.2: 8254 Block Diagram
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9. 8254 Software-Programmable Timer/Counter
LECTURE 25:-
8254 Software-Programmable Timer/Counter 9
Figure 3.3: Control Register format for 8254
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10. Programming the 8254 LECTURE 25:-
8254 Software-Programmable Timer/Counter
Programming the 8254
Each counter is programmed individually by writing
A control word
The initial count
Control word selects
Counter
Mode of operation
Type of operation (read/write)
Type of count (binary/BCD) 10
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11. Programming the 8254 LECTURE 25:-
8254 Software-Programmable Timer/Counter
Programming the 8254
Program sequence 1:
Program control word 1
Program control word 2
Program LSB1
Program LSB 2
Program MSB 1
Program MSB 2
Program sequence 2:
Program LSB 1 11
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12. LECTURE 25:-
THANK YOU
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13. 8254 Modes of Operation LECTURE 26:-
8254 Software-Programmable Timer/Counter
8254 Modes of Operation
Mode 0: Events counter.
Mode 1: One shot pulse
Mode 2: Continuous pulses, one clock pulse wide
Mode 3: Continuous square-wave as long as Gate is 1
Mode 4: Software triggered one-shot pulse
Mode 5: Hardware triggered one-shot pulse 13
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14. Modes of Operation LECTURE 26:-
8254 Software-Programmable Timer/Counter
Modes of Operation
Figure 3.4:-Mode 0: Events counter
(used for system time)
Figure 3.5:- Mode 1: One shot pulse 14
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15. Modes of Operation LECTURE 26:-
8254 Software-Programmable Timer/Counter
Modes of Operation
Figure 3.6:-Mode 2: Continuous pulses
Figure 3.7:-Mode 3: Continuous square-wave 15
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16. Modes of Operation LECTURE 26:-
8254 Software-Programmable Timer/Counter
Modes of Operation
Figure 3.8:-Mode 4: Software triggered one-shot pulse
Figure 3.9:-Mode 5: Hardware triggered one-shot pulse 16
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17. LECTURE 26:-
THANK YOU
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18. 8259 – Programmable Interrupt Controller
LECTURE 27:-
8259 – Programmable Interrupt Controller
8259 – PIC
Interrupts in PC
Interrupts and calls
Programming 8259
Interfacing 8259 in PC 18
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19. 8259 – Programmable Interrupt Controller
LECTURE 27:-
8259 – Programmable Interrupt Controller
What is Interrupt 19
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20. 8259 – Programmable Interrupt Controller
LECTURE 27:-
8259 – Programmable Interrupt Controller
8086/88 Interrupts
256 Interrupts.
Types 00 ……. FF.
Type is provided in a specified timing. 20
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21. 8259 – Programmable Interrupt Controller Interrupt Vector Table
LECTURE 27:-
8259 – Programmable Interrupt Controller
Interrupt Vector Table 21
Figure 3.10: List of designated interrupt for 8086
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22. 8259 – Programmable Interrupt Controller Answering an Interrupt
LECTURE 27:-
8259 – Programmable Interrupt Controller
Answering an Interrupt
Save status
FR, IP, CS
Service the interrupt
Interrupt service routing (ISR) or Interrupt handler
Based on Interrupt vector number
From Interrupt vector table
Four bytes for every interrupt: CS:IP
Return to original position by IRET 22
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23. 8259 – Programmable Interrupt Controller
LECTURE 27:-
8259 – Programmable Interrupt Controller
Difference with Call
CALL FAR can jump to any location (1M range)
Hardware interrupts can come at any time.
Interrupts are maskable.
After CALL only CS:IP is saved
End of routine: RETF vs. IRET. 23
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24. LECTURE 27:-
THANK YOU
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25. 8259 – Programmable Interrupt Controller
LECTURE 28:-
8259 – Programmable Interrupt Controller
Interrupt Categories
Hardware interrupts:
Only 3 pin, but how 256 interrupt?
INTR (in), NMI (in), and INTA (out)
INTR can be masked by CLI / STI
Active high.
80x86 finished instruction.
Push FR, CS, IP
NMI: INT 02.
Software interrupts
INT n
Example: INT 21H (DOS functions) 25
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26. 8259 – Programmable Interrupt Controller
LECTURE 28:-
8259 – Programmable Interrupt Controller
Interrupt and Flags 26
Figure 3.11:- Flag register for 8086
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27. 8259 – Programmable Interrupt Controller Predefined Interrupts
LECTURE 28:-
8259 – Programmable Interrupt Controller
Predefined Interrupts
INT 00 (divide error)
INT 01 (single step)
Set Trap flag (how?)
PUSHF, POP AX, …
Trace in debug
INT 02 (NMI)
INT 03 (breakpoint)
INT 04 (signed number overflow)
INT) instruction
Examine Interrupt vector table.
Examine INT 12H (size of conventional RAM in AX) 27
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28. LECTURE 28:-
THANK YOU
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29. 8259 – Programmable Interrupt Controller
LECTURE 29:-
8259 – Programmable Interrupt Controller
Figure 3.12: 8259 PIC pin diagram 29
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30. 8259 – Programmable Interrupt Controller
LECTURE 29:-
8259 – Programmable Interrupt Controller
Figure 3.13: 8259 PIC Block diagram 30
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31. 8259 – Programmable Interrupt Controller
LECTURE 29:-
8259 – Programmable Interrupt Controller
Figure 3.14: 8259 PIC Block diagram 31
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32. 8259 – Programmable Interrupt Controller
LECTURE 29:-
8259 – Programmable Interrupt Controller
Programming the 8259A
Programmed by Initialization (ICWs) and Operation (OCWs) Command Words.
There are 4 ICWs.
At power-up, ICW1, ICW2 and ICW4 must be sent.
If ICW1 indicates cascade mode, then ICW3 must also be sent. 32
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33. 8259 – Programmable Interrupt Controller
LECTURE 29:-
8259 – Programmable Interrupt Controller
Control Word (initialization)
Table No. 3.1:-8259 Control Word selection 33
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34. 8259 – Programmable Interrupt Controller
LECTURE 29:-
8259 – Programmable Interrupt Controller
Figure 3.15:- Initialization of command word ICW1
LTIM indicates if IRQ lines are positive edge-triggered or level-triggered. 34
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35. 8259 – Programmable Interrupt Controller
LECTURE 29:-
8259 – Programmable Interrupt Controller
Figure 3.16:- Initialization of command word ICW2
These bits determine the vector numbers used with the IRQ inputs.
For example, if programmed to generate vectors 08H-0FH, 08H
is placed into these bit positions. 35
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36. 8259 – Programmable Interrupt Controller
LECTURE 29:-
8259 – Programmable Interrupt Controller
ICW3
Figure 3.17:- Initialization of command word ICW3 36
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37. 8259 – Programmable Interrupt Controller
LECTURE 29:-
8259 – Programmable Interrupt Controller
ICW4
Figure 3.18:- Initialization command word for ICW 4 37
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38. 8259 – Programmable Interrupt Controller
LECTURE 29:-
8259 – Programmable Interrupt Controller
ICW4
Fully nested mode allows the highest-priority interrupt request from a slave to be recognized by the master while it is processing another interrupt from a slave.
AEOI, if 1, indicates that an interrupt automatically resets the interrupt request bit, otherwise OCW2 is consulted for EOI processing. 38
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39. LECTURE 29:-
THANK YOU
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40. 8259 – Programmable Interrupt Controller Masking and Prioritization
LECTURE 30:-
8259 – Programmable Interrupt Controller
Masking and Prioritization
Table No. 3.2:- Address for 8259 OCW (operation command word)
CS^-1 A0
Operation command word
OCW2,OCW3 1
OCW1 x
8259 is not addressed
The Operation Command Words (OCWs) are used to direct the operation of the 8259A. 40
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41. 8259 – Programmable Interrupt Controller
LECTURE 30:-
8259 – Programmable Interrupt Controller
OCW1 is used to read or set the interrupt mask register.
If a bit is set, it will turn off (mask) the corresponding interrupt input
Figure 3.19:- Programming OCW 1 41
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42. 8259 – Programmable Interrupt Controller
LECTURE 30:-
8259 – Programmable Interrupt Controller
Figure 3.20:- Programming OCW2 42
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43. 8259 – Programmable Interrupt Controller
LECTURE 30:-
8259 – Programmable Interrupt Controller
Programming OCW2
Non-specific EOI: Here, the ISR sets this bit to indicate EOI. The 8259A automatically determines which interrupt was active and re-enables it and lower priority interrupts.
Specific EOI: ISR resets a specific interrupt request given by L2-L0.
Rotate commands cause priority to be rotated w.r.t. the current one being processed.
Set priority: allows the setting of the lowest priority interrupt (L2-L0). 43
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44. 8259 – Programmable Interrupt Controller
LECTURE 30:-
8259 – Programmable Interrupt Controller
OCW3
Figure 3.21:- Programming OCW3 44
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45. 8259 – Programmable Interrupt Controller
LECTURE 30:-
8259 – Programmable Interrupt Controller
OCW3
Programming OCW3
If polling is set, the next read operation will read the poll word.
If the leftmost bit is set in the poll word, the rightmost 3 bits indicate the active interrupt request with highest priority.
Allows ISR to service highest priority interrupt.
There are three status registers, Interrupt Request Register (IRR), In-Service Register (ISR) and Interrupt Mask Register (IMR). 45
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46. 8259 – Programmable Interrupt Controller
LECTURE 30:-
8259 – Programmable Interrupt Controller
8259 in PC XT
ICW1: 13H
ICW2: 08H
ICW3: 09H
Figure 3.22:- Chip select decoder of 8259A 46
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47. 8259 – Programmable Interrupt Controller Interrupt Sources in PC
LECTURE 30:-
8259 – Programmable Interrupt Controller
Interrupt Sources in PC 47
Figure 3.23: Sources of hardware interrupt
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48. LECTURE 30:-
THANK YOU
DTEL 48

49. 8251A programmable Communication Interface
LECTURE 31:-
8251A programmable Communication Interface
Introduction
8251A is a USART (Universal Synchronous Asynchronous Receiver Transmitter) for serial data communication.
Programmable peripheral designed for synchronous /asynchronous serial data communication, packaged in a 28-pin DIP.
Receives parallel data from the CPU & transmits serial data after conversion.
Also receives serial data from the outside & transmits parallel data to the CPU after conversion. 49
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50. 8251A programmable Communication Interface
LECTURE 31:-
8251A programmable Communication Interface 50
Figure 3.24: Pin Diagram of 8251A USART
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51. 8251A programmable Communication Interface
LECTURE 31:-
8251A programmable Communication Interface 51
Figure 3.25: Block diagram of the 8251 USART
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52. 8251A programmable Communication Interface
LECTURE 31:-
8251A programmable Communication Interface
Sections of 8251A
Data Bus buffer
Read/Write Control Logic
Modem Control
Transmitter
Receiver
1. Data Bus Buffer
D0-D7 : 8-bit data bus used to read or write status, command word or data from or to the 8251A 52
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53. 8251A programmable Communication Interface
LECTURE 31:-
8251A programmable Communication Interface
2. Read/Write Control logic
Includes a control logic, six input signals & three buffer registers: Data register, control register & status register.
Control logic : Interfaces the chip with MPU, determines the functions of the chip according to the control word in the control register & monitors the data flow. 53
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54. 8251A programmable Communication Interface
LECTURE 31:-
8251A programmable Communication Interface
Input Signals
CS – Chip Select : When signal goes low, the 8251A is selected by the MPU for communication.
C/D – Control/Data : When signal is high, the control or status register is addressed; when it is low, data buffer is addressed. (Control register & status register are differentiated by WR and RD signals)
WR : When signal is low, the MPU either writes in the control register or sends output to the data buffer. 54
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55. LECTURE 31:-
THANK YOU
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56. 8251A programmable Communication Interface
LECTURE 32:-
8251A programmable Communication Interface
Input Signals .
RD : When signal goes low, the MPU either reads a status from the status register or accepts data from data buffer.
RESET : A high on this signal reset 8252A & forces it into the idle mode.
CLK : Clock input, usually connected to the system clock for communication with the microprocessor. 56
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57. 8251A programmable Communication Interface
LECTURE 32:-
8251A programmable Communication Interface
Control Register
16-bit register for a control word consist of two independent bytes namely mode word & command word.
Mode word : Specifies the general characteristics of operation such as baud, parity, number of bits etc.
Command word : Enables the data transmission and reception.
Register can be accessed as an output port when the Control/Data pin is high. 57
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58. 8251A programmable Communication Interface
LECTURE 32:-
8251A programmable Communication Interface
Status register
Checks the ready status of the peripheral.
Status word in the status register provides the information concerning register status and transmission errors.
Data register
Used as an input and output port when the C/D is low
Table No. 3.3:-Operation selection from 8251 CS
C/D WR RD
Operation 1 ×
MPU reads data from data buffer
MPU writes data from data buffer
MPU writes a word to control register
MPU reads a word from status register
Chip is not selected for any operation 58
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59. 8251A programmable Communication Interface
LECTURE 32:-
8251A programmable Communication Interface
3. Modem Control
DSR - Data Set Ready : Checks if the Data Set is ready when communicating with a modem.
DTR - Data Terminal Ready : Indicates that the device is ready to accept data when the 8251 is communicating with a modem.
CTS - Clear to Send : If its low, the 8251A is enabled to transmit the serial data provided the enable bit in the command byte is set to ‘1’.
RTS - Request to Send Data : Low signal indicates the modem that the receiver is ready to receive a data byte from the modem. 59
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60. 8251A programmable Communication Interface
LECTURE 32:-
8251A programmable Communication Interface
4. Transmitter section
Accepts parallel data from MPU & converts them into serial data.
Has two registers:
Buffer register : To hold eight bits
Output register : To convert eight bits into a stream of serial bits.
Figure 3.26: Block diagram of the 8251 Transmission section 60
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61. 8251A programmable Communication Interface
LECTURE 32:-
8251A programmable Communication Interface
Continue…
The MPU writes a byte in the buffer register.
Whenever the output register is empty; the contents of buffer register are transferred to output register.
Transmitter section consists of three output & one input signals
TxD - Transmitted Data Output : Output signal to transmit the data to peripherals
TxC - Transmitter Clock Input : Input signal, controls the rate of transmission. 61
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62. 8251A programmable Communication Interface
LECTURE 32:-
8251A programmable Communication Interface
Continue…
Transmitter section consists of three output & one input signals
TxRDY - Transmitter Ready : Output signal, indicates the buffer register is empty and the USART is ready to accept the next data byte.
TxE - Transmitter Empty : Output signal to indicate the output register is empty and the USART is ready to accept the next data byte. 62
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63. 8251A programmable Communication Interface
LECTURE 32:-
8251A programmable Communication Interface
5. Receiver Section
Accepts serial data on the RxD pin and converts them to parallel data.
Has two registers :
Receiver input register
Buffer register
Figure 3.27: Block diagram of the 8251 Receiver section 63
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64. 8251A programmable Communication Interface
LECTURE 32:-
8251A programmable Communication Interface
Continue..
When RxD goes low, the control logic assumes it is a start bit, waits for half bit time, and samples the line again. If the line is still low, the input register accepts the following data, and loads it into buffer register at the rate determined by the receiver clock.
RxRDY - Receiver Ready Output: Output signal, goes high when the USART has a character in the buffer register & is ready to transfer it to the MPU.
RxD - Receive Data Input : Bits are received serially on this line & converted into a parallel byte in the receiver input register.
RxC - Receiver Clock Input : Clock signal that controls the rate at which bits are received by the USART. 64
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65. Chapter 3 Question Bank LECTURE 32:-
Draw the pin diagram of 8251 and explain various pins.
Write a short note on USART.
Define the following the following errors of 8251
i)Parity error ii) Overrun error iii) Framing error
Write short note on RS-232C serial data standard.
Explain all the modes of 8254 with neat waveforms.
Design a programmable timer using 8254 and Interface 8254 at an address 0080H for counter 0 and write the following programs. The 8086 and 8254 operates at 6MHz & 1.5MHz resp.
i)To generate a square wave of 1ms period
ii)To interrupt the process after 10 ms
iii)To derive the mono-shot pulse with quasistable state of 5ms period.
Draw the architecture of 8259 and explain the facilities available therein.
Explain the initialization command word for 8259 with their formats.
Explain special mask mode & polling mode of 8259.

66. LECTURE 32:-
Summary
8251 (Universal Synchronous Asynchronous Receive Transmit) is an 28 pin IC use for serial communication. It is having three errors as I )parity error ii) overrun error iii)framing error
RS-232 C standard is an it is developed by EIA and used for serial data communication. This standard describes the functions of 25 signals and handshake pins are provided for serial communication.
8254(programmable interval timer/counter)is a 24 pin IC used for generating delay or counter. It is having 5 modes of operation.
8259 is a programmable interrupt controller. It is 28 pin IC which contains interrupt control logic block. ICL helps to arrange the priorities of interrupt and give it to 8086.

67. LECTURE 32:-
THANK YOU
DTEL 67