1. Cell Design Standard Cells Datapath Cells General purpose logic
EE141
Cell Design
Standard Cells
General purpose logic
Can be synthesized
Same height, varying width
Datapath Cells
For regular, structured designs (arithmetic)
Includes some wiring in the cell
Fixed height and width

2. Standard Cell Layout Methodology – 1980s
EE141
Standard Cell Layout Methodology – 1980s
Routing
channel
VDD
signals
Contacts and wells not shown.
What does this implement??
GND

3. Standard Cell Layout Methodology – 1990s
EE141
Standard Cell Layout Methodology – 1990s
Mirrored Cell
No Routing
channels
VDD
VDD M2
Contacts and wells not shown.
What does this implement?? M3
GND
Mirrored Cell
GND

4. Standard Cells Cell height 12 metal tracks
EE141
Standard Cells
N Well
Cell height 12 metal tracks
Metal track is approx. 3 + 3
Pitch = repetitive distance between objects
Cell height is “12 pitch” V DD
Out In 2
Rails ~10
GND
Cell boundary

5. Standard Cells With minimal diffusion routing With silicided diffusion
EE141
Standard Cells
With minimal diffusion routing V DD
With silicided diffusion V DD
Out In
Out In
GND
GND

6. EE141
Standard Cells
2-input NAND gate V DD A B
Out
GND

7. Stick Diagrams Contains no dimensions
EE141
Stick Diagrams
Contains no dimensions
Represents relative positions of transistors V DD V DD
Inverter
NAND2
Out
Out In A B
GND
GND

8. Stick Diagrams Logic Graph j VDD X i GND A B C PUN PDN A j C B
EE141
Stick Diagrams
Logic Graph j
VDD X i
GND A B C
PUN
PDN A j C B
X = C • (A + B) C i
Systematic approach to derive order of input signal wires so gate can be laid out to minimize area
Note PUN and PDN are duals (parallel <-> series)
Vertices are nodes (signals) of circuit, VDD, X, GND and edges are transitions A B A B C

9. Two Versions of C • (A + B)
EE141
Two Versions of C • (A + B) A C B A B C
VDD
VDD X X
Line of diffusion layout – abutting source-drain connections
Note crossover eliminated by A B C ordering
GND
GND

10. Consistent Euler Path X C i VDD X B A j A B C GND EE141
A path through all nodes in the graph such that each edge is visited once and only once.
The sequence of signals on the path is the signal ordering for the inputs.
PUN and PDN Euler paths are (must be) consistent (same sequence)
If you can define a Euler path then you can generate a layout with no diffusion breaks
A B C
C A B
B C A  no PDN
B A C
A C B -> no PDN
C B A A B C
GND

11. OAI22 Logic Graph X PUN A C D C B D VDD X X = (A+B)•(C+D) C D B A A B
EE141
OAI22 Logic Graph X
PUN A C D C B D
VDD X
X = (A+B)•(C+D) C D B A A B
PDN A
GND B C D

12. EE141
Example: x = ab+cd

13. Multi-Fingered Transistors
EE141
Multi-Fingered Transistors
One finger
Two fingers (folded)
Less diffusion capacitance