1. Date of download: 6/6/2016 Copyright © 2016 SPIE. All rights reserved. The block diagram of the CMOS readout circuit structure. Figure Legend: From: Design and experimental verification of a readout integrated circuit for uncooled focal plane arrays Opt. Eng. 2008;47(10):104402-104402-6. doi:10.1117/1.2996015

2. Date of download: 6/6/2016 Copyright © 2016 SPIE. All rights reserved. The readout circuit structure of each pixel. Figure Legend: From: Design and experimental verification of a readout integrated circuit for uncooled focal plane arrays Opt. Eng. 2008;47(10):104402-104402-6. doi:10.1117/1.2996015

3. Date of download: 6/6/2016 Copyright © 2016 SPIE. All rights reserved. The gain curve versus frequency of the transfer function for the CDS circuit. Figure Legend: From: Design and experimental verification of a readout integrated circuit for uncooled focal plane arrays Opt. Eng. 2008;47(10):104402-104402-6. doi:10.1117/1.2996015

4. Date of download: 6/6/2016 Copyright © 2016 SPIE. All rights reserved. The clock timing waveforms of the main driving signals and the output. Figure Legend: From: Design and experimental verification of a readout integrated circuit for uncooled focal plane arrays Opt. Eng. 2008;47(10):104402-104402-6. doi:10.1117/1.2996015

5. Date of download: 6/6/2016 Copyright © 2016 SPIE. All rights reserved. Micrograph of part of the 64×64-element readout chip. Figure Legend: From: Design and experimental verification of a readout integrated circuit for uncooled focal plane arrays Opt. Eng. 2008;47(10):104402-104402-6. doi:10.1117/1.2996015

6. Date of download: 6/6/2016 Copyright © 2016 SPIE. All rights reserved. Block diagram of the testing bench. Figure Legend: From: Design and experimental verification of a readout integrated circuit for uncooled focal plane arrays Opt. Eng. 2008;47(10):104402-104402-6. doi:10.1117/1.2996015

7. Date of download: 6/6/2016 Copyright © 2016 SPIE. All rights reserved. The typical output voltage signal of the readout chip. Figure Legend: From: Design and experimental verification of a readout integrated circuit for uncooled focal plane arrays Opt. Eng. 2008;47(10):104402-104402-6. doi:10.1117/1.2996015

8. Date of download: 6/6/2016 Copyright © 2016 SPIE. All rights reserved. The root mean square voltage and power spectrum of the output noise of the readout chip. Figure Legend: From: Design and experimental verification of a readout integrated circuit for uncooled focal plane arrays Opt. Eng. 2008;47(10):104402-104402-6. doi:10.1117/1.2996015

9. Date of download: 6/6/2016 Copyright © 2016 SPIE. All rights reserved. Output voltage versus photogenerated current. Figure Legend: From: Design and experimental verification of a readout integrated circuit for uncooled focal plane arrays Opt. Eng. 2008;47(10):104402-104402-6. doi:10.1117/1.2996015

10. Date of download: 6/6/2016 Copyright © 2016 SPIE. All rights reserved. Output voltage versus integration time. Figure Legend: From: Design and experimental verification of a readout integrated circuit for uncooled focal plane arrays Opt. Eng. 2008;47(10):104402-104402-6. doi:10.1117/1.2996015