1. Security and Trust Issues in 3D ICs Soha Alhelaly (salhelaly@mail.smu.edu) Advisor Prof. Jennifer Dworak (jdworak@mail.smu.edu)

2. What is a 3D Integrated Circuit? Traditional System Feature size of today’s transistors ≈ 22 nm Distance from chip to chip across a board ≈ 2.2 cm Memory ASIC Processor Board with multiple chips That is 1 million!! What else has this ratio? That’s a big difference!! Let’s stack bare die on top of each other and put them in a single chip package. Can we reduce this ratio to save time and power? Circuit Board Silicon Interposer Processor Memory ASIC Distance between die ≈ 10 μm That’s a Cool and powerful technology Now, SAMSUNG is producing 3D chips A 3D V-NAND presentation package First mass-produced three-dimensional NAND flash chip SAMSUNG website: http://www.samsung.com/global/business/semiconductor/news-events/press-releases/detail?newsId=12990http://www.samsung.com/global/business/semiconductor/news-events/press-releases/detail?newsId=12990

3. Characteristics of the 3D die impact security An entire board in a package Access to all die comes only through the base die Can’t visually inspect die once assembled Can’t remove and analyze die once assembled Overall variability is likely to increase So what does this mean for security? It’s easier to hide things and harder to find them!!

4. Potential 3D Security Issues

5. We are currently focusing on detecting an extra die in the stack What kinds of extra die could be added and what could they do? RF Antenna could be added with an extra die on top of the stack and broadcast the data on the bus RF TX die Extra memory and controller die can save selected data for later extraction. Extra memory and controller die Extra memory and controller die Out of band TSV’s Extra processor die can drive data bus with opposite values when triggered shorting power and ground. Extra processor Extra Die in stack can cause complex Trojans Original Die Stack

6. How can we detect Extra Die in the Stack? Depends on where in the stack extra die are located: top of stack is harder. Potential Strategies: Temperature Profile X-rays or other imaging approaches Voltage drop Side Channel Analysis (Power and Delay) We are currently investigating these strategies For more information Interested in learning more about this project? Soha Alhelaly (salhelaly@mail.smu.edu) Interested in joining our research group? Prof. Jennifer Dworak (jdworak@mail.smu.edu)