1. Pixel structure in Timepix2 : practical limitations June 15, 2010. Vladimir Gromov NIKHEF, Amsterdam, the Netherlands

2. Timepix-2 V.Gromov215/06/10 Gossipo-3: functionality and pixel structure Oscillator 25μm x 10 μm (8%) Logic: counters & control (64%) Analogue Front-end DAC each pixel measures: - hit arrival time → cluster’s drift time (resolution: 1.6ns @ 4bit, range: 25ns @ 12bit) - time-over-threshold → charge deposit (resolution / range: 25ns@8bit) - number of hit (24 bits) triggering options: - external common stop read-out options: - serial read-out of all the pixels other functionalities: - auto clear (no stop signal after expected latency) Time mode Hit Counting mode

3. pixel size: 55 x 55 = 100% Timepix-2 V.Gromov315/06/10 Gossipo-3: Counters & control NAND2BXLTF 3.6x2 x 1 = 7.2 (0.23%) DFFRX2TF 3.6x9.2 x 1 = 33.12 (1.1%) NOR2XLTF 3.6x1.6 x 1 = 5.8 (0.2%) ∑ = 1.5% Hit _detector Fast counter ToT counter_8 Slow counter_12 Controller DFFSX1TF 3.6x8.4 x 4 = 121 (4%) XOR2X1TF 3.6x3.2 x 1 = 11.5 (0.4%) NAND4BX1TF 3.6x2.8 x 1 = 10 (0.3%) MX2X1TF 3.6x3.6 x1 = 13 (0.4%) MX3X4TF 3.6x8 x1 = 29 (1%) AND3X1TF 3.6x2.4 x1 = 8.6 (0.3%) INVX1TF 3.6x1.2 x2 = 8.6 (0.3%) ∑ = 6.7% DFFSX1TF 3.6x8.4 x 8 = 242 (8%) XOR2X1TF 3.6x3.2 x 3 = 34 (1.1%) NAND4BX1TF 3.6x2.8 x 1 = 10 (0.3%) NAND4X1TF 3.6x2.4 x 1 = 8.6 (0.3%) MX2X1TF 3.6x3.6 x1 = 13 (0.4%) MX3XLTF 3.6x6.4 x1 = 23 (0.8%) AND2X1TF 3.6x2 x1 = 7.2 (0.2%) OR2X1TF 3.6x2 x1 = 7.2 (0.2%) INVX1TF 3.6x1.2 x1 = 4.3 (0.14%) ∑ = 11.6% DFFSX1TF 3.6x8.4 x 12 = 363 (12%) XOR3X1TF 3.6x7.6 x1 =27 (0.9%) XOR2X1TF 3.6x3.2 x1 = 11 (0.4%) NAND4BX1TF 3.6x2.8 x1= 10 (0.3%) NAND4X1TF 3.6x2.4 x1 = 9 (0.3%) NOR3X1TF 3.6x2 x1 = 7.2 (0.2%) NAND4X1TF 3.6x2.4 x1= 8.6 (0.3%) MX2X1TF 3.6x3.6 x1 = 13 (0.4%) MX3XLTF 3.6x6.4 x1 = 23 (0.8%) ∑ = 15.6% DFFNSRX2TF 3.6x9.6 x3 = 104 (3.4%) DFFQX1TF 3.6x6.8 x3 = 73 (2.4%) AOI22XLTF 3.6x2.4 x1 = 8.6 (0.3%) OAI2BB2XLTF 3.6x2.8 x1 = 10 (0.3%) OAI32XLTF 3.6x2.8 x1= 10 (0.3%) AOI2BB2XLTF 3.6x2.8 x2 = 20 (0.7%) AO21XLTF 3.6x2.4 x2 = 17 (0.6%) OAI211XLTF 3.6x2.4 x3 = 26 (0.8%) AOI31XLTF 3.6x2.4x2= 16 (0.6%) OAI2BB1XLTF 3.6x2.4 x1= 8.6 (0.3%) NAND3XLTF 3.6x2 x2 = 14 (0.5%) NAND3BXLTF 3.6x2.4 x2 17 (0.6%) AND3XLTF 3.6x2.4 x1 = 8.6 (0.3%) NOR3XLTF 3.6x2 x1= 7.2 (0.2%) NOR3BXLTF 3.6x2.4x1 = 8.6 (0.3%) NAND2XLTF 3.6x1.6 x1 = 6 (0.2%) OR2X1TF 3.6 x2 x1 = 7.2 (0.2%) NAND2XLTF 3.6x1.6 x2 = 11.5 (0.4%) OR2X1TF 3.6x2 x2 = 14.4 (0.5%) NOR2BXLTF 3.6x2x2= 14 (0.5%) NOR2XLTF 3.6x1.6x1= 5 (0.2%) INVXLTF 3.6x1.2 x4 = 17 (0.6%) ∑ = 14.1% ∑ = 49.5% (ideal) 64 % (layout) 8% oscillator 28% (Front-end +THR Dac+ config. memory)

4. Timepix-2 V.Gromov410/03/10 Timepix2: super pixel structure Local Fast oscillator (600MHz) Preamp & Discri 4 bit Fast counter 8 bit ToT counter 12 bit Slow counter 2 bit pixel ID (hard wired) pixel A pixel B pixel C pixel D 7 bit Super_pixel ID (hard wired) hit data taking phase read-out phase Clock (40MHz) Counter Fast Counter ToT Counter Slow Reset Preamp_out Hit (asynchronous) Common Stop (Trigger) Token ToT B C D A 2 x 2 Clk (40MHz) start stop ToT counter = 8bit ??? Slow counter = 12 bit ???? 26bit 33bit Ref. = Gossipo

5. Timepix-2 V.Gromov510/03/10 Super pixel: shared Local Oscillator configuration Local Fast oscillator (600MHz) Preamp & Discri & Threshold DAC FE_pixel_1 8 bit ToT counter 12 bit Slow counter 2 bit pixel ID (hard wired) hit_1 hit_2 Counter Block_1 7 bit Super_pixel ID (hard wired) Counter Block_2 Counter Block_3 Counter Block_4 Shared LO Block hit_3 hit_4 4 bit Fast counter OR start stop Clk (40MHz) clk (640MHz) AND ` FE_pixel_2 FE_pixel_3 FE_pixel_4 B C D A 2 x 2 Clk Fanout Control 4 LO → 1 LO & Fanout + Control

6. Timepix-2 V.Gromov610/03/10 Super pixel: with shared counter blocks Preamp & Discri 2 bit pixel ID pixel_1 8 bit ToT counter 12 bit Slow counter 4 bit Fast counter 2 bit Memory (pixel ID)r hit hit_1 hit_2 Counter Block_1 pixel_2 pixel_3 pixel_4 2 bit Super_pixel ID Counter Block_2 Counter Block_3 Counter Block_4 Multiplexers MX1 MX2 MX3 MX4 hit_1 hit_2 hit_3 hit_4 hit_3 hit_4 4-to-1multiplexer MX4X1TF (3.6 μm x 8.4 μm) hit_1 hit_2 hit_3 hit_4 hit_1 hit_2 hit_3 hit_4 hit_1 hit_2 hit_3 hit_4 Clk (40MHz) start / control stop Shared LO block hit_1 hit_2 hit_3 hit_4 fast (640MHz) clock Control shared counter block → dead time reduction extra logic → Fanout + Control

7. Timepix-2 V.Gromov701/06/10 Triggered / Continuous data acquisition mode TR A ↓ Common stop of the counter FE1 FE2 FE3 FE4 Cnt2 Cnt3 Cnt4 Cnt Tx Col A Col B off chip Cnt Data taking phase A = waiting for the TR A rst T3, Q3 T4, Q4 start 1 start 2 start 4 start 3 T2, Q2 T1, Q1 cluster Mem A Mem B Mem C Mem D Cnt1 Token. A TOKEN ID1 ID2 ID3 ID ID4 Mem E 33-bit 20MHz bus 33-bit 20MHz bus Cnt Mem A Mem B Mem C Mem D Mem E EoC buffer B EoC buffer A 40-bit 320MHz bus 8 x Token. B Data taking phase B TR B ↓ Common stop of the counter rst Features: Triggered mode → Common stop is generated by an external device (Trigger) Continuous mode → Common stop is generated on-chip regularly every 2 n ● 25ns (n=1..12) - auto clear if no Common stop after expected latency - only active pixel data is transmitted to the EoC memory block (sparse data readout ) via 32-bit @ 20MHz buses - pixel ID (9bit + 7bit) to be added to the data - EoC memory is required ( dead area on the periphery) - dead time is ToT (100ns … 6 μs) + pixel-to-EoC readout time (depends on the number of active pixels in the column and bandwidth of the readout bus) pixel-to- EoC readout ↓ Dead time Data acquisition interval (adjustable) up to 102μs (12 bits @ 40MHz) - common time reference (TR) - no BX (25ns) associated data selection - sparse readout with zero suppression Column Drain architecture

8. Mx32 Mx1 TBUF 32 TBUF 2 Timepix-2 V.Gromov801/06/10 Data bus: 33-bit @20MHz M1 M3 M2 1μm1μm 0.5μm 33 lines @ (1 μm + 0.5μm) = 49.5 μm 0.024fF /μm 0.15fF/μm Rs M2 = 0.0639 Ω/□ 0.024fF /μm 0.15fF/μm A A A A A A A A A A A A 110μm Column width 256 ● 55μm = 1.4cm 32-bit @20MHz bus TBUF 1 Mx1 3-state buffer TBUFX8TF 3.6 μm x 5.6 μm 4-to-1multiplexer MX4X1TF 3.6 μm x 8.4 μm 33 ch → 13% (total area) Uin Ubuf_out Uline_out (1.4cm) Settling time ~ 25ns ↓ 20MHz Bandwidth the Data bus response worst case: length= 1.4cm in1 in2 in3 in4 Common Enable