1. FGM peer CDR FGE FPGA - 1 Berlin, April 6, 2004 FGE FPGA Olaf Hillenmaier Magson GmbH

2. FGM peer CDR FGE FPGA - 2 Berlin, April 6, 2004 Telemetry Interface CMD Receiver Write Decoder CMD ADR CMD DATA Wr.Adr. Parity Error Sync. Error Data CollectorTMH Data SR Data CollectorTML Data SR XYZ data Status XYZ data Status 1Hz Sync. CLK CLK Unit Mag.Start (128Hz) Serial Data TML Serial Data TMH CLK Serial CMD

3. FGM peer CDR FGE FPGA - 3 Berlin, April 6, 2004 Configuration registers X Y Z X Y Z X Y Z ADC ConstantDAC ConstantOffsets X Y Z DAC Registers Mode Register Excitation On/Off Std.Mode/Calibr. FB Relays TML Rate Filter Mode CMD DATA CMD DATA CMD DATA CMD DATA CMD DATA

4. FGM peer CDR FGE FPGA - 4 Berlin, April 6, 2004 DAC Interface Register 18 Bit DAC Accu. 18 Bit DAC Module 12 Bit DAC Module 12 Bit DAC signed Integer 18 Bit Register (for calculation) (one channel) DAC corse DAC fine Arithmetic unit MUX / SplitModule Auto feed back/ Calibration CMD DATA ADC Accu

5. FGM peer CDR FGE FPGA - 5 Berlin, April 6, 2004 Excitation / ADC CTR Excit. Phase Module ADC CTR Excit.On/Off (Phase) Start Excit. Sample (Number sampling periods) ADC Sample Add.End ADC ser. Data SR 14 Expand Module 24Bit ACCU 24Bit Arithm. Unit (one channel) CMD DATA CMD DATA

6. FGM peer CDR FGE FPGA - 6 Berlin, April 6, 2004 Arithmetic Unit XYZ ADC Accu XYZ DAC Accu XYZ ADC Coefficient XYZ DAC Coefficient XYZ Offset TML Frequency XYZ TMH XYZ TML Arithmetic Unit Filter mode

7. FGM peer CDR FGE FPGA - 7 Berlin, April 6, 2004 FPGA Development Status FGE BB Implementation in ProASIC A500K180 (24%) FPGA design routed in RT54SX72S ~ 50% (without ADC accumulator, filter calculation) Excitation, ADC CTR, ADC and DAC Interface, ADC and DAC Accumulator tested in VEX RT54SX32S FPGA Telemetry and Arithmetic unit tested with ProASIC