1. May 10-14, 2010CALOR2010, Beijing, China 1 Readout electronics of the ALICE photon spectrometer Zhongbao Yin *, Lijiao Liu, Hans Muller, Dieter Rohrich, Iouri Sibiryak, Bernhard Skaali, Alexandre Vinogradov, Dong Wang *, Yaping Wang *, Fan Zhang *, and Daicui Zhou * * Institute of Particle Physics Huazhong Normal University, China

2. May 10-14, 2010CALOR2010, Beijing, China 2 Outline The ALICE PHOS The readout electronics –Avalanche Photo-Diode (APD)+ Charge Sensitive Pre-amplifier (CSP) –Front-End Electronics (FEE) board –Trigger Region Unit (TRU) and Trigger OR (TOR) Summary

3. May 10-14, 2010CALOR2010, Beijing, China 3 ALICE A Large Ion Collider Experiment at LHC 18 detector sub- systems Dedicated to searching for QGP Comprehensive study of hadrons, electrons, muons and photons

4. May 10-14, 2010CALOR2010, Beijing, China 4 PHOS 1 Module=3584 crystals P b WO 4 5 PHOS modules 100 degrees in amzimuth -0.12 to 0.12 in eta APD and preamplifier attached to crystal Radiation length of 0.89cm Interaction length of 19.5cm Moliere radius of 2.0 cm Crystal dimensions of 2.2x2.2x18cm 3 Temperature coefficient of ~-2%/  C Operating temperature of –25  C Each crystal equipped with one APD+CSP To measure photons,  0 ’s and  ’s in a broad p t range from ~ 100 MeV/c up to 80 GeV/c.

5. May 10-14, 2010CALOR2010, Beijing, China 5 PHOS electronics overview Least count energy 5 MeV Dynamic range of 5 MeV to 8 GeV with optimum energy resolution Timing resolution ~ 2ns at 2 GeV Individual APD bias setting L0 and L1 triggers

6. May 10-14, 2010CALOR2010, Beijing, China 6 APD+CSP 1 APD mounted on back Sensitivity: 1 V/pC U CSP /E = 26.7  V/MeV at M APD =50 and –25  C max. input charge 8 pC ENC ~400e for C APD =100 pF Power dissipation 62 mW PHOS uses the same APDs which had been co-developed with Hamamatsu for the CMS experiment The Hamamatsu S8664-55 is a Si APD diode in ceramic package with sensitive area of 5x5 mm 2 Considerable differences in individual APD gain with the same reverse-bias voltage The nominal gain M=50 corresponds to a reverse bias voltage of about 330- 390 V at –25 o C CSP

7. May 10-14, 2010CALOR2010, Beijing, China 7 Final FEE product 32 ch. dual gain shapers, 64 readout channels 10 bit ADC’s (within ALTRO) 10MHz 14 bit dynamical range 5MeV-80GeV 32 HV regulators, 10 bit for APD bias with a precision of 0.20V in the range of 210-400V. Thus, the APD gain variation can be limited to ~0.66% Fast OR signal produced by 100 ns 2x2 summing shaper on FEE for trigger purposes GTL + readout and control bus 5.5W, 349x210 mm 2

8. May 10-14, 2010CALOR2010, Beijing, China 8 Shaper 32 semi-gaussian shaper low and high gain with ratio of ~16 dynamic range of 14 bit cover energy range from 5 MeV to 80 GeV 2  s peaking time Low gain of 0.427, 78MeV- 80GeV High gain of 6.85, 5MeV- 5GeV Differential input to ALTRO 10bit ADC

9. May 10-14, 2010CALOR2010, Beijing, China 9 FEE Board Controller Response as a slave to the DCS subsystem of the RCU Default communication via the parallel GTL bus I 2 C serial RCU protocol also implemented Monitoring of voltage, current and temperature; interrupt when parameters out of range HV bias control and monitoring via SPI bus

10. May 10-14, 2010CALOR2010, Beijing, China 10 Performance at T10 4% gain balance by individually adjusting APD bias The energy resolution is quite good even operating at –17  C It is expected to have a better energy resolution at the nominal operating temperature of –25  C

11. May 10-14, 2010CALOR2010, Beijing, China 11 Trigger Region Unit 112 FastOR signals produced by 100 ns 2x2 summing shaper on FEE Transmitted to TRU via differential cables 112 analogue inputs -> 12 bit ADCs @ 40 MHz Digitized data -> processed in FPGA within 300 ns LVDS link TOR 1 readout bus 40 bit RCU-> DAQ/HLT TRU: 12 layer board with Virtex-5 14 x ADS 5281 ( octal ADC 12 bit)

12. May 10-14, 2010CALOR2010, Beijing, China 12 FPGA internal Process in TRU 28 x PWO 16 x PWO 91 combinations ( 91 parallel calculations in FPGA ) 4x4 (=2x2 F-OR) 1 TRU region 448 crystals >Threshold? L0-Yes 1.) Every 25 ns: 4x4 space sums in 91 parallel instances 2.) Time sum 5 bunches 3.) OR over all Time sums Comparison over single threshold L0-yes: 91 space-time sums get stored in a TRU buffer Trigger data

13. May 10-14, 2010CALOR2010, Beijing, China 13 TRU board controller First registers: Temperature/Voltage/Current monitoring ADS5270 pedestal correction Trigger thresholds Trigger enable/disable Interrupt and corresponding mask/thresh. Registers Trigger data readout “fake Altro”

14. May 10-14, 2010CALOR2010, Beijing, China 14 Trigger OR = TOR (to become global level-1 decision box) 40 x RJ45 connectors for TRU 4 trigger outputs to CTP Power Virtex 4 FPGA (bottom) DCS card connector (bottom) Local TRU decisions for L0, externally or’d by TOR See Lijiao Liu’s presentation on “Commissioning of PHOS trigger”

15. May 10-14, 2010CALOR2010, Beijing, China 15 PHOS L0 trigger results Timing result of PHOS L0 testPHOS Module2 triggered by PHOS L0

16. May 10-14, 2010CALOR2010, Beijing, China 16 Summary The full readout electronics of ALICE PHOS has been presented. The performance studies show that PHOS readout electronics are overall in very good shape. PHOS is taking data smoothly……