1. Development of SOI Pixel Detectors Toshinobu Miyoshi - Institute of Particle and Nuclear Studies, KEK On behalf of SOI collaboration 1 VIPS 2010 - Workshop on Vertically Integrated Pixel Sensors,2010/4/22-4/24

2. 2 -Overview -DATA Acquisition System -Pixel detectors 1. Integration-type pixel detector 2. Counting-type pixel detector -Pixel detectors in FY09 - current issues -summary Outline

3. 3 1. Integration-Type Pixel detector (INTPIX) 2. Counting-Type Pixel detector(CNTPIX) FY09-1 INTPIX3b INTPIX4 CNTPIX4 2005 2006 2007 2008 2009 2010 FY05 MPW (VDEC) PIXELTEG (INTPIX) SOI pixel detector development –Overview- FY06 KEK MPW 0.15um Process INTPIX1 CNTPIX1 FY07 KEK MPW 0.2um Process INTPIX2 CNTPIX2 FY08 INTPIX3 CNTPIX3 KEK (High Energy Accelerator Research Organization) has developed several detector chips since 2005. There are two type of pixel detectors:

4. Ethernet ROOT GUI software PC SEABAS=Soipix EvAluation BoArd with SiTCP* -packaged chip is mounted on sub-board -65MHz 12-bit ADC (only for INTPIX) - 4 ch 12bit DAC -User FPGA controls -SiTCP(network processor) for TCP/IP -light weight detector system (portable) Pixel detector chip sub-board Packaged chip * T. Uchida and M. Tanaka, “Development of a TCP/IP Processing Hardware”, IEEE Nuclear Science Symposium, San Diego, USA, Oct. 29 - Nov. 4, 2006, NSSproc. N33-6, 1411 – 1414. 4 DATA Acquisition System (Since 2008) All the data acquisition are done with the SEABAS

5. 1.Integration type pixel detector(INTPIX) FY07 FY08 INTPIX2 Chip size 5mm x 5mm 5 INTPIX3 FY09-1 INTPIX3b INTPIX2 w/o Buried P-well (BPW) INTPIX3 & 3b w. BPW

6. INTPIX2,3,3b pixel circuit 6 CMOS Active Pixel Sensor with a storage capacitor INTPIX2

7. INTPIX2(w/o BPW) block diagram 128x128 pixels 7 Photograph

8. INTPIX3&3b (w. BPW) block diagram All the peripheral circuits are covered by BPW IO pad 8

9. 9 INTPIX3 (FY08) and INTPIX3b (FY09-1) Evaluate SOI pixel with BPW 16 pixel layouts with/without BPW 1 region = 64 x 32 pixels Chip layout 5mm

10. INTPIX3 INTPIX3b INTPIX3 & INTPIX3b -Pixel layout (16 patterns) 10 The same as INTPIX2 BPW 1p+ implant Large BPW 1p+ implant Small BPW

11. 11 Test results with (a) IR laser (b) X-ray

12. IR(980nm) laser response (INTPIX2---w/o BPW) Back gate effect? Red color Expected curve (depletion increase) 12 IR laser = 980nm  penetration depth ~100um back bias=50V  depletion depth ~ 100um (calculation) However, signal output start decreasing more than 10V

13. IR(980 nm) laser response (INTPIX3---w. BPW) IR laser = 980nm  penetration depth ~100um back bias=50V  depletion depth ~ 100um (calculation) INTPIX2 INTPIX3 BPW on the peripheral circuit is effective 13 w/o BPW in a pixel

14. 14 window focused inside Pulsed 1064 nm YAG:Nd laser (base width~10ns) Univ. of Tsukuba IR(1064nm) laser response INTPIX3---w. BPW INTPIX3 region 7 - Signal increases up to 130 V (near breakdown voltage) - Back-gate effect is suppressed IR laser = 1064nm  penetration depth ~3mm

15. KEK-PF BL-14A Monochromatic X-ray SOI (SEABAS) XZ stage Beam slit Beam filter(Zr,Mo) 15 X-ray test (Monochromatic X-ray ) X-ray with 12-18.5 keV was used. To evaluate -Sensitivity -Gain -Detection efficiency

16. X-ray response Signal-ped[ADU] Count[8x8 pixels x 1000event] INTPIX integration time 100us, Vback=100V RSTV=750mV 18.5keV monochromatic X-ray : Intensity ~ 2.3photons/pixel /100us, beam spot size = 0.4mm2 X-ray absorption (@Si150um&18.5keV-X-ray) ~17% (  ~40% in total event should be x-ray event ) INTPIX3 region7 INTPIX3b region6 Count[8x8 pixels x 1000event] 16 Dark level signal *w/o charge-sharing correction Difference: BPW size, transistor position, metal position Dark level signal Evaluation results(Preliminary) Gain ~7.9  V/e- (INTPIX3-7), ~ 21.7  V/e- (INTPIX3b-6) The gain is smaller with larger BPW size in a pixel dE/E ~25% (FWHM)@25C o,w/o CDS, statistical fluctuation Detection efficiency --- to be calculated (analysis ongoing) 0 100 200 300 400 500 600 700 Condition:

17. 17 Summary of BPW study - “BPW in a pixel” helps us to solve the back gate issue, but the gain decreases. - Even if the BPW is not in a pixel, the back gate effect might be tolerate to some back bias voltages ( to be studied). - When the number of transistor is small, “BPW in a pixel” is effective because the BPW size can be reduced. - When the number of transistor is large and the BPW covers all the transistors, the gain decrease is a critical problem. - Once the potential of the outer BPW ring in a pixel is fixed, charge collection efficiency might severely decrease. So, the outer BPW ring in a pixel should be floating.  INTPIX4 and CNTPIX5(later topics) - In “3D-SOI” (applying ZyCube micro-bump), “BPW in a pixel” is effective because we can reduce the number of transistors in the lower chip.

18. FY07 FY09-1 CNTPIX2 CNTPIX4 2. Counting type pixel (CNTPIX) 18 (a) X-ray response (CNTPIX2) (b) Red laser response (CNTPIX4)

19. - We have tried another kind of pixel; photon-counting type pixel since FY06 run. (CNTPIX1@FY06,CNTPIX2@FY07...) - Explore high-rate, high-resolution X-ray counting chip with SOI technology. - Follow architecture of successful Medipix2 chip. 19 Counting -Type Pixel (CNTPIX) Medipix

20. Counting-Type Pixel (CNTPIX2) : FY07 Charge Amp Dual Discri Counter Energy window and counting in each pixel. 20 w/o BPW

21. p-n junctions Analog 16b Counter 9b Register DDL 128 x 128 pixels CNTPIX2 pixel layout and photograph 10.4mm 60um # of transistors ~600 transistors/pixel 21

22. X-ray response (Intensity dependence) Total counts increased with intensity Relative intensity (uA) Total counts in the figure X-ray tube Cu K_alpha ~8keV (Rigaku FR-D) Photodiode was used for intensity measurement 22 However, we requires CNTPIX with BPW for the more quantitative evaluation due to the back-gate effect CNTPIX2 (w/o BPW)

23. CNTPIX4 4 kinds of Pixel Block 72x216(15,552) pixels. 5.0 x 15.4 mm 2 chip size 64 x 64 um 2 pixel size IO pads are located in one side for stitching. BPW in a pixel 4 kinds of Pixel Block 72x216(15,552) pixels. 5.0 x 15.4 mm 2 chip size 64 x 64 um 2 pixel size IO pads are located in one side for stitching. BPW in a pixel 23 stitching 23

24. 24 CNTPIX4 Pixel Circuit Data & Control words are shifted downwards. 24

25. 25 Red laser (635nm) response Metal mask - Circuit works successfully - No major problem in the circuit -Evaluating noise level, pulse laser response (ongoing) CNTPIX4 sub-board with chip COL(0-71) ROW(0-215) 100 0

26. 26 The other chip in FY09-1 INTPIX4 – new integration type pixel

27. 27 INTPIX4 15.4 mm 10.2 mm - Largest chip so far - Pixel size: 17x17  m - # of pixels: 512 x 832 pixels - 13 Analog Out (13x512x64) - CDS circuit in each pixel - To use 13 analog output in parallel, New “fast” readout system board is required (SEABAS2)  the design started. It will complete in this summer

28. Pixel Layout Single BPW 17  m -Pixel size was reduced to 17  m -Circuit is based on PMOS -2 types of pixels: Single BPW or floating BPW ring Pixel circuit 28

29. 29 FY09-1 INTPIX3b INTPIX4 CNTPIX4 2005 2006 2007 2008 2009 2010 FY05 MPW (VDEC) PIXELTEG (INTPIX) New Design (FY09-2) FY06 KEK MPW 0.15um Process INTPIX1 CNTPIX1 FY07 KEK MPW 0.2um Process INTPIX2 CNTPIX2 FY08 INTPIX3 CNTPIX3 FY09-2 INTPIX3c CNTPIX5

30. 30 New design (FY09-2) INTPIX3C Updated version of INTPIX3b CNTPIX-TEG chip Including Amplifier, shaper and discriminator The Bare chip arrived at KEK before a couple of days. Packaged chip will arrive soon. Wafers for 3D chip (2 sets) will start the process soon. KEK 3D chip CNTPIX 3D chip Based on CNTPIX5 CNTPIX5 chip Update version of CNTPIX 4 (see the next page)

31. 31 Counting Type Pixel (CNTPIX5) D D

32. CNTPIX4 CNTPIX5 The same pixel size: 64x64 um 2 BPW in a pixel Counter option: 9bit x 2 or 18bit Preamplifier + Shaper Binning mode: 2x2 pixels  9b x 8 store Features of CNTPIX5 16 bit Counter Discri x 2 Preamp Control Logics Comparison CNTPIX4 and CNTPIX5 32 Bare chip just arrived at KEK!

33. 33 Current Issues 1. Breakdown voltage 2. Radiation tolerance

34. Back gate effect suppressed well. Next  higher back bias voltage must be applied to gain full depletion in 260um thickness wafer  Breakdown protection INTPIX3,CNTPIX3 : breakdown voltage ~130V 1. Breakdown Voltage 34 I-V / CNTPIX2&3 140V cntpix2 cntpix3 120V uA 1 7

35. Breakdown protection With BPW structure, maximum back bias voltage is limited by breakdown voltage (~130V) (1) apply BPW on guard ring to avoid potential concentration (2) apply field plate above guard ring (3) 3D-SOI also help us to increase breakdown voltage INTPIX3c P+ Field plate (METAL1) BOX 35 Pixel region Guard ring (x3) Bias ring IO pad (IO ring) Nsub Pixel region Multi-guard ring Bias ring IO (upper chip) Nsub … box

36. SOI is Immune to Single Event Effect thanks to buried oxide (BOX) ＋－ ＋－ ＋－ ＋－ ＋－ ＋－ ＋－ ＋－ ＋－ ＋－ ＋－ Bulk Device Gate Gate Oxide Si ＋－ ＋－ ＋－ ＋－ SOI Device Gate ＋－ ＋－ ＋－ Si Buried Oxide Depletion Layer 36 However, the BOX is not so strong to total Ionization Dose due to thick BOX layer Gate Si Buried Oxide ＋＋＋＋＋ Trapped Holes 2. Radiation Tolerance 36 Back bias

37. 37 By adding the BPW layer, Electric field in the BOX is reduced and possibility of charge recombination will increase. However, it is not enough especially for high-energy physics experiment! By adding the BPW layer, Electric field in the BOX is reduced and possibility of charge recombination will increase. However, it is not enough especially for high-energy physics experiment! Radiation Tolerance and BPW X-ray Irradiation (X-ray tube, Cu-8keV) 37

38. P-SiN Al-pad Si adhesive Lower Chip Upper Chip Copyright 2009 ZyCube Co. Ltd. 38 Radiation tolerance enhancement 1. We are discussing process improvement with new idea using BPW and BNW 2. 3D-SOI is also a solution: Transistor on upper chip will not be much affected to oxide charge. * BNW : buried N-well

39. 39 Summary We have developed mainly two types of pixel detector: -Integration-Type pixel Thanks to BPW, it is operated with more than 100 V of the back bias voltage. Single photon event from X-ray was observed and the response was evaluated. -Counting-Type pixel The circuit developed successfully. Architecture for stitching worked with no major problem. Larger INTPIX detector and counting-type pixel detector with multi-function was developed. Evaluation is ongoing. Feasibility study for X-ray and high-energy physics application with INTPIX4 and CNTPIX5 will start.

40. 40 2010 (FY10) works We will have MPW run twice. Common R&D -Design: BPW optimization in a pixel, 3D integration -radiation hardness, charged particle beam test - Thinning (~100um) + operation under full depletion Integration-type pixel - smaller pixel size with CDS circuit -X-ray application in collaborating with KEK-IMSS (Institute of Material Structure Science) -Counting-Type pixel -Multi-functional photon-counting pixel detector - evaluation test with IR laser and X-rays - High-energy physics application  ”SBPIX“ for the future Belle upgrade Other kinds of pixels (challenging works!) -Including APD or DEPFET sensors or column ADC circuit on SOI… * HEP: Thinner XR: Thicker * TAIKO process can grind up to 50um (from the web)

41. 41 Supplement

42. 42 -Hardware ： KEYENCE LE-4000 LASER DISPLACEMENT METER Mitutoyo MEASURING MICROSCOPE(stage) -Method ： Cut wafer 0 point set at left-upper corner,10mm pitch measurement from circuit side -Place ： block 1 ～ 6 Block 1,3 ： 40x80mm^2 Block 4,6 ： 40x60mm^2 Block 2 ： 30x80mm^2 Block 5 ： 30x60mm^2. Except block 6, : right uppper corner used. 20mm Wafer distortion measurement

43. 43 Wafer distortion (preliminary) Due to remaining distortion during manufacture process, in 40x80mm wafer 0.4mm in the maximum