1. Samuel Silverstein, SYSF ATLAS calorimeter trigger upgrade work Overview Upgrade to PreProcessor MCM Topological trigger

2. 2 ATLAS trigger and L1Calo

3. 3 Phase I upgrades to L1Calo PreProcessor:  New mixed-signal MCM with FPGA Jet-Energy processor  Daughter board replacements with high performance, modern FPGAs Topological processing with Regions of Interest (RoI)  Send RoI coordinates, threshold bits and ET over backplane (real-time data path)  Multi-Gbit optical transmission of RoIs from L1 subsystems to a new topology algorithm processor Integration with upgraded calorimeter electronics  Digital pre-processor and feature extraction subsystems for e.g. improved electron identification

4. 4 PreProcessor MCM functionality Peak finder FIR filter No consecutive non-zero values Used to identify bunch crossing ADC Analog trigger tower sum 0.1  0.1 (5 samples) serialiser  To CP To JEP (4x4) (1/4)

5. 5 PreProcessor MCM upgrade FPGA (Spartan 6) 2 Dual-channel FADCs (AD9218) Current MCM New MCM 4 ADCsserializers ASIC Adjustable delay Bottom Top

6. 6 Jet and cluster algorithms 0.4 x 0.4 0.6 x 0.6 0.8 x 0.8 Jet algorithm: EM cluster algorithm (  /had similar): Local maximum "Environment"

7. 7 CPUCPU CMMCMM TCMTCM CMMCMM 14 CPMs One quadrant per crate CPUCPU CMMCMM TCMTCM CMMCMM 16 JEMs Two quadrants per crate Digital algorithm processors JEM CPM JEP: 2 crates CP: 4 crates 2 merger modules (CMM) collect real-time results from all CPMs/JEMs in the crate

8. 8 Results merging: CMM 25 point-to-point backplane links from each JEM/CPM to each CMM Current speed 40 MHz (25 bits/BC)  e.g. 8  3-bit multiplicities + 1 Parity bit CMM Backplane merger layers System-level merging Crate-level merging Readout To CTP

9. 99 CMM replacement: CMX Readout to DAQ and ROI RODs (Glink emulation) SNAP12 Optical links: 12-fiber bundles (SNAP12 or or similar), 6.4 Gbit/s LVDS outputs to CTP Virtex 6 HX565T Backplane data from JEMs/CPMs (160 MHz) LVDS links for crate-to- system merging SNAP12 VME CPLD VME -- Must be backward-compatible with existing CMM

10. 10 CP3 CMXCMX CMXCMX CP2 CMXCMX CMXCMX 5  8 = 40 CP fibers Data transmission CMX to TP CP1 CMXCMX CMXCMX JEP1 CMXCMX CMXCMX CP0 CMXCMX CMXCMX EM EM/  JetEnergy JEP0 CMXCMX CMXCMX 5  2 = 10 Jet fibers 2 Energy fibers (256b) L1 TP processing unit L1 TP processing unit Link regrouping and duplication 8 muon fibers from 4 MIOCTs 60 fibers on five SNAP12 links Scalable TP architecture

11. 11 TP DeMUX and extraction SNAP12 Roi DeMUX and extraction stage (~1.5 BC)  RoIs Jet RoIsCluster RoIsE T, ME T CoordinatesThreshJet E T CoordinatesThresholdsEM E T  ET ET CoordinatesThresh Data available in parallel for 1 BC Muons arrive later....

12. 12 Topo algorithm candidates AlgorithmObjectsSorting?Comments cluster/jet overlap e/  + jets no Jet/jet overlapjetsJ140 + another J100  2 leptons, jets, MET yes Likely: use the two highest-E T objects  RR Jet METn jets no Vector E T sum HTHT n jets, leptonsObject E T sum Inv mass2 objects no Evaluate all possible pairs in parallel Inv transverse mass1 object, MET Aplanarity, sphericityjets?complicated...

13. 13 TP real time data path Roi DeMUX and extraction stage  RoIs Jet RoIsCluster RoIsE T, ME T Algorithm 1 TM( , ME T ) Algorithm 2 e + Jets, non-overlap Algorithm 3  (e, e) CTP output bits Algorithms select and process data in parallel Parallel output to CTP at 80 MHz

14. 14 Upgraded L1 overview Illustration of proposed trigger upgrades, with one of several possible connection scenarios. EM calorimeter digital readout Muon detector EM & hadronic calorimeters L1 accept

15. 15 DPP and FEX architectures DPPM FEXM 2x hadr. cables 8x EM input cables 4x EM output fiber cables 10x raw EM input fiber cables ROIs to TP (1-2 fibers) 12-fiber O/E modules (6.4 Gbit/s) DPP FPGAs EM/  FPGAs JET FPGA DPPMDPPM DPPMDPPM DPPMDPPM DPPMDPPM DPPMDPPM DPPMDPPM DPPMDPPM DPPMDPPM DPPMDPPM DPPMDPPM DPPMDPPM DPPMDPPM SSMSSM FEXMFEXM FEXMFEXM FEXMFEXM FEXMFEXM FEXMFEXM FEXMFEXM FEXMFEXM FEXMFEXM FEXMFEXM FEXMFEXM FEXMFEXM FEXMFEXM SSMSSM DPPMDPPM DPPMDPPM DPPMDPPM DPPMDPPM DPPMDPPM DPPMDPPM DPPMDPPM DPPMDPPM DPPMDPPM DPPMDPPM DPPMDPPM DPPMDPPM SSMSSM SSM: "Shelf Service Module" Functions: Timing, trigger distribution Readout functions etc....

16. 16 Phase-2 concept L0: produce RoIs to seed tracking trigger L1: combined Calo, muon and tracks

17. 17 L1Calo upgrade activities at SU Phase-1 hardware coordination (Sam) High-speed link studies FPGA firmware studies  G-link emulation in Virtex-6  Migration of existing CMM code to CMX Future involvement  Extensive firmware work for Phase-1, especially CMX and topological processing  Hardware contribution to Phase-1 or Phase-2

18. 18 Multi-Gbit Link tests

19. 19 Glink emulation in Virtex 6

20. 20 Outlook SYSF has a strong role in a large scale, extended upgrade program for L1Calo Already performing useful upgrade R&D Strong commitment to hardware and firmware projects for Phase-1 and Phase-2  Should keep us busy past 2020!