1. Overvoltage Protection Module 12-15 June 2013 Ringberg Castle Bartlomiej Kisielewski, Piotr Kapusta1 - Overview - Functionality - LT4356-2 Surge Stopper for ASIC voltages - LT2912 Voltage Monitor for Gate and Steering voltages - communication with MCU (microcontroller) - time schedule

2. 12-15 June 2013 Ringberg Castle Bartlomiej Kisielewski, Piotr Kapusta2

3. 12-15 June 2013 Ringberg Castle Bartlomiej Kisielewski, Piotr Kapusta3 Surge Stopper DHP_IO, DCD_DVDD DHP_CORE, DCD_AVDD ALL DOMAIN e.g. Digital, Analog, Gate, Steering Functionality (from Stefan paper) To Be Defined ? Serial readout by MCU Voltage Monitor

4. 12-15 June 2013 Ringberg Castle Bartlomiej Kisielewski, Piotr Kapusta 4 Digital Domain Gate Domain Steering Domain All voltages will be fixed by resistor networks !!!

5. 12-15 June 2013 Ringberg Castle 5 Piotr Kapusta, Bartlomiej Kisielewski Analog Domain Gate Domain Steering Domain All voltages will be fixed by resistor networks !!!

6. 12-15 June 2013 Ringberg Castle Bartlomiej Kisielewski, Piotr Kapusta6 AV2 VSOURCE ST8 GATE_OFF ST5,6,7 GATE_ON x 3 ST2 CLEAR_OFF ST1 CLEAR_ON ST ? VDRIFT ST9,10,11 VCCG x 3 ST13 VBP (-3V,+5V) (-3V,-13V) (7V,25V) (0V,5V) ST3 VBULK (-12V,-5V) (-80V) (-10V,+1V) (0V,7V) (5V,15V) (1.8V/3.3V)(1.8V) (1.1V) (1.8V) (0.35V) AV1 AVDD_DCD DV1 DVDD_DCD DV3 DHPCORE AGND (Analog Ground) AV3 DCD_AMPLOW DV4 DVDD_SW AV4 REFIN_DCD DV2 DHPIO (1.2V) DGND (Digital Ground) SGND (Steering Ground) ST4 VGUARD (-7V,0V) DEPFET SUBSTRATE – must be connected to the lowest of all supply voltages SWB: 3.3V, SWB18:1.8V GGND (Gate Ground) GATE DIGITALANALOG ?

7. Digital Domain Analog Domain Gate Domain Steering Domain Xilinx CPLD uC signals Digital optocouplers Status bits are sent to the uC, reset (re-enable) bits are sent to the domains. Digital control of the Over Voltage Protection board 12-15 June 2013 Ringberg Castle Bartlomiej Kisielewski, Piotr Kapusta7

8. DVDD DCD 1.8V/1A DHPCORE 1.2V/580mA DHPIO 1.2V DVDD SW 3.3V/24mA from Voltage Regulator to Front End Electronics FAULT(3.5V) FAULT (1.6V) FAULT(3.5V) FAULT Digital Domain Piotr Kapusta, Bartlomiej Kisielewski 8 OPTOS OR AND DFLOP OPTOS 12-15 June 2013 Ringberg Castle 8 Disable if OVEnable OV OPTOS DGND OPTOS Reset OV

9. 12-15 June 2013 Ringberg Castle Bartlomiej Kisielewski, Piotr Kapusta9 Over Voltage Protection for critical ASIC supplies Transistor-switch

10. 12-15 June 2013 Ringberg Castle Bartlomiej Kisielewski, Piotr Kapusta10 Over Voltage Protection

11. 12-15 June 2013 Ringberg Castle Bartlomiej Kisielewski, Piotr Kapusta11 Vin Vout Regulator enable Domain enable Overvoltage Fault

12. 12-15 June 2013 Ringberg Castle Bartlomiej Kisielewski, Piotr Kapusta12 Over Voltage Protection for Gate and Steering supplies SSR-Solid State Relay SSR

13. 12-15 June 2013 Ringberg Castle Bartlomiej Kisielewski, Piotr Kapusta13

14. 12-15 June 2013 Ringberg Castle Bartlomiej Kisielewski, Piotr Kapusta14

15. 12-15 June 2013 Ringberg Castle Bartlomiej Kisielewski, Piotr Kapusta15 -3V -13V GATE ON DISABLE

16. 12-15 June 2013 Ringberg Castle Bartlomiej Kisielewski, Piotr Kapusta 16 Glitch Immunity of LTC2912

17. 12-15 June 2013 Ringberg Castle Bartlomiej Kisielewski, Piotr Kapusta17 Summary 1.the idea of OVP module is almost fixed and schematic is almost ready 2. PCB design just started 3.prototype should be ready 2013 and tested with PS system 4.comments are welcome !

18. 12-15 June 2013 Ringberg Castle Bartlomiej Kisielewski, Piotr Kapusta18 Thank You !

19. 12-15 June 2013 Ringberg Castle Bartlomiej Kisielewski, Piotr Kapusta 19 Back up

20. 12-15 June 2013 Ringberg Castle Bartlomiej Kisielewski, Piotr Kapusta 20 Surge Stopper Over Voltage Protection Surge Stopper

21. 12-15 June 2013 Ringberg Castle Bartlomiej Kisielewski, Piotr Kapusta 21 Voltage Monitor Latch Fault Solid State RelayVoltage Monitor Over Voltage Protection

22. 12-15 June 2013 Ringberg Castle Bartlomiej Kisielewski, Piotr Kapusta22 from White Book

23. 12-15 June 2013 Ringberg Castle Bartlomiej Kisielewski, Piotr Kapusta23

24. 12-15 June 2013 Ringberg Castle Bartlomiej Kisielewski, Piotr Kapusta24 Detection of undervoltage and overvoltage events for GATE ON (-3V, -13V) - -3V -13V