1. The MOS capacitor.
(a) Physical structure of an n+-Si/SiO2/p-Si MOS capacitor, and (b) cross section
(c) The energy band diagram under charge neutrality and (d) the energy band diagram at equilibrium (note that the surface of the p-type substrate near the oxide interface has become weakly inverted).

2. Energy band diagrams for the n+-Si/SiO2/p-Si capacitor
(a) The case for equilibrium. Electrons from the n+ gate transfer to the p-Si substrate, resulting in a positive gate and a negative depletion region in the substrate.
(b) The accumulation condition. Here a negative voltage is applied to the gate with respect to the substrate such that holes accumulate at the silicon–to–silicon dioxide interface.
(c) The situation for a positive 2-V step voltage. immediately after the application of the voltage.
(d) With time, electrons generated in the transition region are trapped in the potential well at the interface until steady state is reached.

3. CV characteristics for the n+-Si/SiO2/p-Si capacitor
Circuit for measuring the capacitance of a MOS capacitor
Capacitance-voltage characteristic for a MOS capacitor at low and high frequencies.

4. Schematic diagram of the structure of an n-channel silicon-based MOSFET
The channel width W, length L, and oxide thickness tox are shown.
The symbols S, G, D, and B represent the source, gate, drain, and substrate (body) respectively.

5. Cross section of an n-channel FET and Band diagrams
(a) Cross section of an n-channel FET
(d)
(b) The energy band diagram at equilibrium.
(c) The channel charges, electrons, accumulate in the bulk near the oxide interface.
(d) The energy band diagram along the channel of the device .

6. A particular MOSFET example
With source, substrate, and drain connected
The energy band diagram along cross section A-A¢ at equilibrium (black) and under bias (colored)
The energy band diagram along the channel for three values of VGS.

7. The energy bands in the semiconductor and Schematic circuit symbols
The energy bands in the semiconductor and Schematic representations (circuit symbols) for
(a) The enhancement NFET (b)The enhancement PFET (c) The depletion NFET (d) The depletion PFET.

8. The energy band diagram of the NFET
The energy band diagram of the NFET across the channel (a) and along the channel (b) with zero voltage between the drain and the source.

9. The energy band diagram of the NFET under gate and drain biases
With a voltage on the drain with respect to the source, the depletion region width varies along the channel. So does the voltage across the channel at any given point.
(b) The energy band diagrams normal to the gate at source and at drain. Here the drain voltage is higher than the source voltage, so the “depth” of the channel varies along its length.
(c) The energy band diagram along the channel with no voltage on the drain with respect to the source, and with positive bias applied drain to source.

10. The energy band diagram of the NFET under gate and drain biases
The energy band along the channel for three different values of VDS.
The current saturates because, as the drain voltage increases, the slope (and thus the electric field) increases faster at the drain end, but at thesource end, there is little change. Thus the current is limited by the field at the source end.
The ID-VDS characteristics of a typical MOSFET.
The threshold voltage for this MOSFET is 0.5 V.

11. The Electric Fields and Resistance in MOSFETs
The NFET. Longitudinal and transverse electric field directions are indicated.
Schematic of an NMOS indicating the channel resistance Rch, the source resistance RS, and the drain resistance RD.

12. The saturation current and saturation voltage on set of pinch-off.
As Vds↑(over Vdsat), pinch-off point moves toward source
Ids remains essentially the same because for Vds>Vdsat, V at pinch-off point remains at Vdsat.

13. The ID-VDS characteristics of the NFET
The predicted current (solid lines) is only valid up to the point where VDS = VGS - VT .
After that, the current saturates (black dashed lines)
The ID-VDS characteristics of the NFET from the simple model.
For this device W/L = 5, tox = 4 nm, C¢ox = 8.63 × 10-3 F/m2, and mn = 500 cm2/V×s.

14. Illustration for current saturation
Illustration for current saturation. (a) The conduction band edge along the channel bends more at the drain
end than at the source end for large drain voltage VDS. (b) Since the longitudinal field is proportional to the
slope of EC, the field changes rapidly at the drain end for increasing values of VDS but not at the source end.
(c) The field at the source end is constant as VDS increases beyond a certain point; thus the current is
constant as well.
Figure 7.20
7-20

15. Channel-length Modulation
With and without channel-length modulation
Experimental ID-VDS characteristics for an n-channel MOSFET for three values of gate voltage. The current
actually increases with increasing VD in the “current saturation” region because of channel-length modulation.
As Vds↑(over Vdsat), pinch-off point moves toward source
Ids remains essentially the same because for Vds>Vdsat, V at pinch-off point remains at Vdsat.
L changes to L’ (L’<L)
 channel length modulation

16. Effects of transverse field
The effect of the transverse electric field on the mobility and drain current.
The electrons in the channel collide with the “walls” of the channel.
(b) The energy band diagram shows that the walls are potential barriers at the oxide interface and the barrier of the depletion region in the semiconductor is sloped.
(c) Comparison of ID-VDS characteristics for the different transverse fields. The currents reduce at the higher transverse field and higher mobility reduction.
(c)