1. Development of SOI pixel sensor 28 Sep., 2006 Hirokazu Ishino (Tokyo Institute of Technology) for SOIPIX group

2. Outline Motivation Introduction to the SOI detector performance of the SOI pixel TEG summary and plan

3. SOIPIX collaborators KEK Detector Technology Project : [SOIPIX Group] Y. Arai(*)、Y. Ikegami、Y. Ushiroda、 Y. Unno、O. Tajima、T. Tsuboyama、 S. Terada、M. Hazumi、H. Ikeda A 、 K. Hara B 、H. Ishino C 、T. Kawasaki D 、H. Miyake E Gary Varner F, Elena Martin F, Hiro Tajima G, M. Ohno H, K. Fukuda H, H. Komatsubara H, J. Ida H KEK、JAXA A 、U. Tsukuba B 、TIT C 、 Niigata U. D 、Osaka U. E, U. Hawaii F, SLAC G, OKI Elec. Ind. Co. H

4. Motivation Vertex detectors play an essential role in particle physics –precise decay position measurements of the heavy quarks and leptons Silicon On Insulator (SOI) is one of the techniques usable for future high energy experiments. –radiation hard no parasitic NPNP structure, therefore no latch- ups. thin active transistor, insensitive to SEU –can be a pixel detector w/o bump bonding – high-resistive handle wafer for radiation detection

5. SOI detector design + + + + + + − − − − − −

6. Overview of our SOI detector Fully-Depleted CMOS SOI fabricated by OKI Electric Industry Co. Ltd. –commercial technology with 150nm rule –thin Si layer (~20nm) + metal gate OKI adopts Unibond wafers from SOITEC, France –Top Si: Cz, ~18Ωcm, p-type, ~40nm thickness –Buried Oxide (BOX): 200nm thickness –handle wafer: Cz, high-resistive with > 1kΩ no type assignment, however, identified by I-V measurements, shown later. original thickness 650  m, thinned to 350  m and plated with Al (200nm).

7. SOI wafer production (UNIBOND TM, SOITEC)

8. SOI pixel process step flow Handling wafer p+ n+ Handling wafer Box SOI 650um ① After Gate stack formation ② Box Window photo lithography and etching ③ Source/Drain Implantation followed by S/D annealing and Salicidation Handling wafer ④ 1 st ILD (interlayer dielectrics) filling and CMP planarization

9. SOI pixel process step flow Handling wafer ⑤ Contact etching Handling wafer ⑥ Contact plug filling and 1 st Metal formation 650um Al p+ n+ 250~350um ⑦ 3 ~ 5Metal formation followed by Backside polishing and Al coating Handling wafer

10. Diode TEG Metal contact & p+ implant Al

11. I-V characteristics of the handle wafer substrate is N-type ~700Ωcm ~6✕10 12 cm -3 BIAS (V) |Current (A)| n+ - BACK P+ - BACK

12. SOI TEG submitted in 2005 2.5 x 2.5 mm 2 Chips –Transistor p-MOS and n-MOS transistors of different parameters the characteristics are measured radiation test has been performed –Circuit preamp, Q2T etc. –Strip Silicon strip sensor for studying its basic performance –pixel 32 x 32 matrix of 20 x 20  m 2 pixels correlated double sample circuit –reset -> integrate -> readout

13. Pixel TEG 6"  MPW wafer 2.5 mm (chip) 20  m (pixel)

14. Pixel TEG CMOS Active Pixel Sensor Type 20  m x 20  m 32 x 32 pixels

15. Pixel layout Window for Light Illumination (5.4 x 5.4 um 2 ) p+ junction Storage Capacitance (100 fF)

16. Pixel IV character V break ~ 100 V I = 40  A, T = 1 min corner of the bias ring  Smooth the corner and move the ring inward at next submission. Vback(V) Iback(  A) Hot Spot observed with infrared camera

17. Pixel detector image Plastic Mask Laser (670 nm) Vdet = 10 V Exposure Time = 7  s

18. V det = 10 V W depletion ~ 44  m Q ~ 3500 e (0.6 fC) Expected signal amplitude was observed for  -ray. Pixel detector signal of  rays from 90 Sr

19. Back gate effect Back gate Bias (V) Threshold Voltage (V) Back Gate Signal disappears at 16V Consistent with SPICE simulation.

20. Bulk: n- (~6 x 10 12 cm -3 ) BOX (200 nm) NMOS (5  m wide p+, 1 x 10 20 cm -3 ) D = (80, 5, 2  m) Backbias (0-100 V) 350  m Back gate effect simulation The p+ implant near the NMOS can reduces the back gate effect. ENEXSS : 3D TCAD Simulator

21. Summary and Plan We have started R&D of the SOI pixel detector with OKI Elec. Ind.Co. A pixel detector with a 32 x 32 matrix of 20 x 20  m 2 pixels has been fabricated and tested. –Photo images are taken successfully –beta rays are successfully detected. Back gate effect can be removed by placing p+ implant near the transistors. –the distance and shape are being optimized using ENEXSS 3D TCAD simulator We will submit next TEG on Dec.

22. backup

23. Contact & Sheet Resistance [Sheet R] n+ : 33  /square p+ : 136  /square [Contact] (0.16x0.16um 2 ) n+ : 87  p+ : 218  Hi-R (> 1k  cm) Std. wafer (p+, ~13  cm) Std. wafer (p+, ~13  cm) Hi-R (> 1k  cm) p+ contact n+ contact