1. Selcuk Cihangir, Fermilab LCWS 2007, DESY 1 SOI, 3D and Laser Annealing for ILC S.Cihangir-Fermilab Representing Contributors from: Fermilab, Bergamo, Cornell, Purdue More details-Talks by: Ron Lipton at SiD Workshop at Fermilab and Oxford Ray Yarema at CERN Atlas-CMS Electronics Workshop

2. Selcuk Cihangir, Fermilab LCWS 2007, DESY 2 SOI (Silicon-on-Insulator) devices 3D and SOI Driving Technologies SOI Activities at Fermilab: –OKI process –American Semiconductor FLEXFET process 3D Activities at Fermilab: –VIP1 chip for ILC Other Activities at Fermilab: –Thinned, edgeless sensors –Laser annealing –Simulation Outline

3. Selcuk Cihangir, Fermilab LCWS 2007, DESY 3 Silicon-On-Insulator Buried oxide (200nm) Bulk CMOS SOI CMOS Isolation from the bulk silicon: Suppression of bottom junction  Lower parasitic capacitance and therefore faster switching and lower power consumption… Enabling operation at higher temps (250 o C) Lower SEU rate. Denser layout (100% diode fill factor)

4. Selcuk Cihangir, Fermilab LCWS 2007, DESY 4 SOI (Cont) Industry accepted overall improvement: 25% faster 50% lower power consumption 10% smaller die size Applications: High Speer Processors- IBM and Motorola: Power PC AMD Athlon-64 Graphic Processor- Sony/IBM/Toshiba: PlayStation 3 High-speed Serial Data Communiation- Mitsubishi: 10 GBps SERDES Ultra Low Power SoC (System on a Chip)- OKI Solar cell watch Satellite systems, spacecraft electronics And HEP…..

5. Selcuk Cihangir, Fermilab LCWS 2007, DESY 5 SOI is formed by bonding a thin active circuit layer on a substrate (handle wafer) that has an oxide layer (~200 nm) on the surface. The handle wafer can be high quality, detector grade silicon, which opens the possibility of integration of electronics and fully depleted detectors in a single wafer with very fine pitch and little additional processing. (Soitech illustration) Steps for SOI wafer formation Active BOX Substrate (detector material) SOI (Cont) Common method of SOI production:

6. Selcuk Cihangir, Fermilab LCWS 2007, DESY 6 SOI - handle wafer engineering: Wafer thinning, bonding and alignment Edgeless sensors Three dimensional (vertical) integration of electronics and sensors –Reduce R, L, C for higher speed –Reduce chip I/O pads –Provide increased functionality –Reduce interconnect power and crosstalk Through wafer via formation and metallization New Detector Technologies This gives ways to new technologies which are applicable to HEP detectors, ILC in particular: Via using oxide etch process (Lincoln Labs) SEM of 3 vias using Bosch process 3D Integration

7. Selcuk Cihangir, Fermilab LCWS 2007, DESY 7 Sensors: Thinned, edgeless Chip fabricated in OKI 0.15  m SOI process –Includes sensor and one layer of electronics for electron microscope Chip being designed in American Semiconductor 0.18  m SOI process (SBIR) –With pixel sensor layer and one or more electronics layers for ILC vertex detector 3D chip (VIP1) being fabricated in MIT LL 0.18  m SOI multi-project run. –3 tier demonstrator chip for ILC vertex detector Bonding Technologies (being explored) –Cu-Sn bonding of FPIX chips/sensors –DBI bonding of 3D chips to MIT sensors Laser annealing (Cornell) Simulations Group Initiatives

8. Selcuk Cihangir, Fermilab LCWS 2007, DESY 8 We are producing a set of thinned, “edgeless” sensors at MIT-LL as a initial test of these concepts Produce a set of detectors thinned to 50-100  m for beam and probe tests. –Validate process –Understand performance –Measure the actual dead region in a test beam Masks designed at FNAL –Test structures –Strip detectors (12.5 cm and ~2 cm) –FPiX2 pixel detectors (beam tests) –Detectors to mate to 3D chip Wafers due in September Sensor Studies

9. Selcuk Cihangir, Fermilab 9 Strip detectors Fpix2 pixel detectors Strip detectors 3D test detectors Test structures MIT-LL Wafer designed at FNAL Due ~September

10. Selcuk Cihangir, Fermilab LCWS 2007, DESY 10 Backside implanted after thinning, before front side wafer processing, laser annealed after processing High resistivity silicon wafer, thinned to 50- 100 microns, full depletion, large signal Active edge processing Minimal interconnects, low node capacitance SOI Concept for HEP Advantages: Low capacitance, no parasitic charge Rad hard (> 1MRad) Low Power, low noise 100% diode fill factor 2. American Semiconductor 0.18  m SOI process (Flexfet) Signal diappears at Vb~16V 1. OKI 0.15 micron SOI process Fermilab Involvement:

11. Selcuk Cihangir, Fermilab LCWS 2007, DESY 11 Fermilab Involvement 1. OKI 0.15  m SOI process (Mambo SOI X-Ray Chip) Counting pixel detector plus readout circuit Maximum counting rate ~ 1 MHz. Reconfigurable counter/shift register 12 bit dynamic range Limited peripheral circuitry Drivers and bias generator Array size 64x64 pixels 350 micron detector thickness Fermilab has submitted a design to a KEK sponsored multi project run at OKI which incorporates diode formation by implantation through the BOX. The chip incorporates a 64 x 64 26 micron pitch 12 bit counter array for a high dynamic range x-ray or electron microscope imaging. Max 13  m implant pitch is determined by the “back gate” effect where the topside transistors thresholds are shifted by handle potential Just received! To be tested at Laser Test Stand. Image by SEM.

12. Selcuk Cihangir, Fermilab LCWS 2007, DESY 12 Fermilab Involvement 2. American Semiconductor 0.18  m SOI process (Flexfet) Signal diappears at Vb~16V Substrate voltage acts as a back gate bias and changes the transistor threshold - like another gate. Requires minimum ~15 micron diode spacing to control surface potential. Optimization is on-going, to be tested. Also, possibility of a pinning layer to shield the analog pixel from digital activity. Bottom gate shields the transistor channel from charge buildup in the BOX caused by radiation, as well as from the voltage on the substrate and removes the Back Gate Voltage problem. Fermilab designed for ASI a demonstration SOI Pixel cell with voltage ramp for time marker, sampling for crossing time, analog pulse height and counter for timestamp. All simulated. from Y. Arai (KEK)

13. Selcuk Cihangir, Fermilab 13 VIP1 Chip 3D chip at MIT LL 0.18  m SOI multi-project run Goal - demonstrate ability to implement a complex pixel design with all required ILC properties in a 20 micron square pixel. Previous technologies limited to very simple circuitry or large pixels. Three levels (tiers) of transistors, 11 levels of metal in a total vertical height of only 22  m. Key features: Analog pulse height, sparse readout, high resolution time stamps. Time stamping and sparse readout occur in the pixel. Hit address found on array perimeter. 64 x 64 pixel demonstrator version of 1K x 1K array. Edgeless sensor to be bonded later. Vias

14. Selcuk Cihangir, Fermilab 14 Analog Time Stamp Data sparsification VIP1 Chip (Cont) Front end power ~ 1875  W/mm 2 (before cycling) 175 transistors in 20 µm pixel. Due in August.

15. Selcuk Cihangir, Fermilab LCWS 2007, DESY 15 After thinning a backside contact must be formed. This is usually done by implantation and high temperature furnace annealing - which will destroy the front side CMOS SOI circuitry. An alternative is laser annealing of the backside implantation, which limits the frontside temperature to less than 500 o C. Use a raster scanned eximer laser to melt the silicon locally – this activates the implant and repairs the implantation damage by re-crystallizing the silicon. Diffusion time of phosphorus in molten silicon is much less than cooling time therefore we expect ~uniform distribution in melt region. Laser Annealing Oak Ridge studies of melt depth vs laser energy To study and qualify this process we took a sample of Run2b HPK, low leakage 4x10 cm 2, strip detectors and reprocessed them: backgrind by ~50 microns to remove back implant and aluminization, polish, re-implant detector using 10 KeV phosphorus at 0.5 and 1.0x10 15 /cm 2, laser anneal and measure CV and IV characteristics. AMBP - 0.8, 1.0, 1.2 J/cm 2, 248 nm laser Cornell - 1.0 J/cm 2 305 nm laser

16. Selcuk Cihangir, Fermilab LCWS 2007, DESY 16 Laser Annealing Results (Cornell-Fermilab) Preliminary V bias (Volts) I leak (microAmps)

17. Selcuk Cihangir, Fermilab LCWS 2007, DESY 17 SIMS Measurements Secondary Ion Mass Spectroscopy provides implant depth profiles by analysis of ions ejected from the surface upon ion bombardment. Two samples, before and after 1.2 J/cm2 248 nm laser anneal: Goal was >2x10 19 concentration Melt depth ~300 nm. Laser melt depth is close to expectation, phosphorus concentration close to expectation. Additional sintering at 400 o C and “forming gas” treatment should improve leakage. Plan to explore leakage current as a function of implantation dose, laser energy and sensor thickness.

18. Selcuk Cihangir, Fermilab LCWS 2007, DESY 18 In addition to what were mentioned above: Can we retain good, low leakage current, detector performance through the CMOS topside processing? How does the charge in the BOX due to radiation and potential of the handle wafer affect the operation of the top circuitry? How does topside digital circuitry affect the pixel amplifier? Simulations: 3D device simulation tools (Silvaco) - extremely useful to understand charge collection, back gate, and digital/analog coupling effects. More to do!

19. Selcuk Cihangir, Fermilab LCWS 2007, DESY 19 Vertically integrated (3D) electronics are becoming available. Much of this technology is ideally suited to HEP vertex detectors. Fermilab is exploring –Monolithic 3D Circuitry –SOI sensors –Wafer bonding technologies With focus on ILC, but also looking at applications in LHC, x-ray imaging, … The technology has promise for X-ray detectors, electron microscope focal planes, imaging, and astronomy. Final Words! (For now) More to come and to say in the near future….

20. Selcuk Cihangir, Fermilab LCWS 2007, DESY 20 Extras

21. Selcuk Cihangir, Fermilab LCWS 2007, DESY 21 SOI detector development is being pursued by Fermilab at two different foundries: OKI in Japan, and American Semiconductor Inc. (ASI) in US. The two processes have different characteristics as seen below. Process 0.15  m Fully-Depleted SOI CMOS process, 1 Poly, 5 Metal layers (OKI Electric Industry Co. Ltd.). SOI wafer Wafer Diameter: 150 mm , Top Si : Cz, ~18  -cm, p-type, ~40 nm thick Buried Oxide: 200 nm thick Handle wafer: Cz 、 >1k  -cm (No type assignment), 650  m thick (SOITEC) BacksideThinned to 350  m, no contact processing, plated with Al (200 nm). Process 0.18  m partially-Depleted dual gate SOI CMOS process, Dual gate transistor (Flexfet), No poly, 5 metal (American Semicondutor / Cypress Semiconductor.) SOI wafer Wafer Diameter: 200 mm , Handle wafer: FZ>1k  -cm (n type) BacksideThinned to 50-100  m, polished, laser annealed and plated with Al. OKI ProcessASI Process Fermilab SOI Detector Activities