1. EE586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu

2. Lecture 27 Decoders

3. Row Decoders Collection of 2 M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder

4. Static Decoder Design  Implementing a wide NOR function in complementary CMOS is impractical.  Pseudo-NMOS is one option  Power dissipation is an issue  Split into two or more logic layers  Segments of the address are decoded in a first logic layer called the predecoder.  A 2 nd layer of logic then produces the final word-line signals.

5. Hierarchical Decoders A 2 A 2 A 2 A 3 WL 0 A 2 A 3 A 2 A 3 A 2 A 3 A 3 A 3 A 0 A 0 A 0 A 1 A 0 A 1 A 0 A 1 A 0 A 1 A 1 A 1 1 Multi-stage implementation improves performance NAND decoder using 2-input pre-decoders

6. Optimization  Calculate the total capacitance of the word lines  Specify the effective fan-out of the decoder path.  Apply logical effort analysis  The word lines are normally held low  Only optimize the rising transition  Skewed gate

7. Dynamic Decoders Precharge devices V DD  GND WL 3 2 1 0 A 0 A 0 GND A 1 A 1  WL 3 A 0 A 0 A 1 A 1 2 1 0 V DD V V V 2-input NOR decoder 2-input NAND decoder

8. 4-input pass-transistor based column decoder Advantages: speed (t pd does not add to overall memory access time) Only one extra transistor in signal path Disadvantage: Large transistor count 2-input NOR decoder A 0 S 0 BL 0 1 2 3 A 1 S 1 S 2 S 3 D

9. 4-to-1 tree based column decoder Number of devices drastically reduced Delay increases quadratically with # of sections; prohibitive for large decoders buffers progressive sizing combination of tree and pass transistor approaches Solutions: BL 0 1 2 3 D A 0 A 0 A 1 A 1

10. Reliability and Yield

11. Redundancy Memory Array Column Decoder Row Decoder Redundant rows Redundant columns Row Address Column Address Fuse Bank :

12. Error-Correcting Codes Example: Hamming Codes