1. S.Zucca a,c, L. Gaioni b,c, A. Manazza a,c, M. Manghisoni b,c, L. Ratti a,c V. Re b,c, E. Quartieri a,c, G. Traversi b,c a Università degli Studi di Pavia b Università degli Studi di Bergamo c INFN Pavia d Università degli Studi di Pisa e INFN Pisa 8th International Meeting on Front-End Electronics FEE 2011 Bergamo, 23-27 May 2011 Analog front-ends for monolithic and hybrid pixels developed with a 3D CMOS process

2. FEE 2011- Bergamo, 23-27 May 2011 Outline SuperB experiment and SVT Layer0 requirements Vertical Integration (3D) CMOS Technologies Analog FE for Apsel VI 3D MAPS chip Why are they so attractive for HEP applications? Issue for large matrices: voltage drop on analog VDD/GND lines. 3D Analog FE for Superpix1 hybrid pixels chip Comparison with the Apsel VI analog FE Fine tuning system for the threshold correction Conclusion and future plans DNW MAPS and hybrid pixels in 3D technology General description

3. FEE 2011- Bergamo, 23-27 May 2011 The SuperB factory, an high luminosity e + -e - collider intended for HEP experiments, has been recently funded by the Italian Ministry for Education, University and Research. SuperB factory Two possible approaches for the SuperB Layer0 at full luminosity: Silicon Vertex Tracker very similar to that of the 5 layer BaBar experiment, completed by a Layer0 very close to the IP (about 1.5 cm) to improve the vertex resolution. Other requirements: Low material budget (<1% X 0 ) Fine granularity (50 μm pitch) CMOS MAPS: can provide low material budget and small pitch. Hybrid Pixels: more mature technology, with somewhat worse material budget features.

4. FEE 2011- Bergamo, 23-27 May 2011 In wafer level 3D processes, multiple layers of planar devices are stacked and interconnected using inter-layer connections. Vertical Integration (3D) CMOS Technologies Advantages for HEP particle pixel detectors: The analog section (and the sensor) do not share the same substrate with the noisy digital readout. Less material in the IP: monolithic structure of the final chip enables post-process thinning. Dead area reduction: the readout electronics can be designed with virtually no peripheral circuits. Higher functional density more complex pixel readout chain (i.e. sparsified, triggered readout techniques). Apsel VI and Superpix1 have been designed in the Globalfoundries- Tezzaron 130 nm 3D CMOS process.

5. FEE 2011- Bergamo, 23-27 May 2011 DNW MAPS DNW MAPS and hybrid pixels in 3D Technologies The inversely biased DNW acts as a collecting electrode. Hybrid pixels A readout chain is used for Q-V conversion gain decoupled from C D NMOS analog FE devices are built-in in the deep N-well. PMOS can be included in the design and placed in a separate layer charge collection efficiency close to 100%. Back to back assembled devices from two chips, by means of bump bonding techniques. They feature: high SNR 100% fill factor no crosstalk between the digital readout electronics and the sensor Large material budget innovative direct bonding techniques (Zyptronix or TMicro/ZyCube) In 3D design the use of two layers provides a lot of functionality in the pixel cell. Digital section DNW sensor Analog section Digital section Analog section 1 st Layer 2 nd Layer sensor

6. FEE 2011- Bergamo, 23-27 May 2011 In-pixel logic for a time-ordered readout Complex in-pixel logic can be implemented without reducing the pixel collection efficiency (thanks to 3D integration) even improving the readout performance (readout could be data push or triggered). Courtesy of F. Morsani (INFN PI) Timestamp (TS) is broadcast to pixels and each pixel latches the current TS when fires. Matrix readout is TS ordered  A readout TS enters the pixel and an HIT-OR-OUT is generated for columns with hits associated to that TS  A column is read only if HIT- OR-OUT=1  DATA_OUT is generated for pixels in the active columns with hits associated to that TS.

7. FEE 2011- Bergamo, 23-27 May 2011 Apsel VI front-end architecture First stage: charge PA with a C FB countinously discharged by an NMOS biased in deep subthreshold region. Second stage: RC-CR shaper with a transconductor feedback network: TIER1 (bottom) TIER2 (top) V bl chip wide distributed by an external voltage reference (not affected by voltage drop issues) Voltage drop effects reduction on the channel-to-channel dispersion of the DC voltage at the shaper output (V bl ) Third stage: comparator (placed on the top tier along with the in-pixel readout logic).

8. FEE 2011- Bergamo, 23-27 May 2011 Charge Preamplifier Two local feedback networks (M4,M5 and M6,M7) to increase the small signal resistance at the node C. C p value is a trade-off between noise and bandwidth. C M FB is used to discharge C FB after the particle hit. DC gain=84 dB F -3dB = 40 kHz

9. FEE 2011- Bergamo, 23-27 May 2011 Shaping stage Cascode input stage and output source follower. First order RC-CR shaping stage: t p : peaking time The transconductor keeps the circuit in the correct bias point and set the output waveform peaking time at the designed value. It can be demonstrated that, in order to obtain an output waveform with the desired t p (constant at the varying of the input signal amplitude), the following equations must be satisfied: A 0 : open loop DC gain f 0 : -3dB cutoff frequency

10. FEE 2011- Bergamo, 23-27 May 2011 Shaping stage Mirrored load transconductor with source degeneration resistance. Since C 2 value has to be small (≈ 50 fF) for area occupancy reasons, Gm value must be very low (≈ 20 nS) to obtain the desired t p (≈ 300 ns) I transc ≈ 10 -9 A Standard solutionSource degeneration solution Mirrored load transconductor : Higher I transc Wider linear range

11. FEE 2011- Bergamo, 23-27 May 2011 Voltage drop on analog VDD/GND lines May be an issue with large matrices of relatively current-hungry detectors  V d =15/20 mV (typ/max) Voltage drop on the AVDD and AGND lines causes changes in some pixel current sources, in particular in the shaper input branch and in the transconductor. These current changes lead to a degradation of the front-end performance (i.e. charge sensitivity and peaking time). Apsel VI features: I analog_cell =25 μA 128x100 pixels matrix for the next run Considering the case of a larger matrix (i.e. 256x256 elements), supplied from both sides, we obtain the following voltage drop on AVDD and AGND: AVDDperipheral AVDDpixel AGNDpixelAGNDperipheral M. Manghisoni, E. Quartieri et al.,“High Accuracy Injection Circuit for Pixel-Level Calibration of Readout Electronics” presented at the 2010 IEEE Nuclear Science Symposium Conference, Knoxville, USA, October 30 - November 6 2010. I =120 nA I sib ≈120 nA I transc ≈ 2.5 nA

12. FEE 2011- Bergamo, 23-27 May 2011 Effects on the shaper output waveform Voltage drop is simulated as a symmetrical voltage variation in the analog power (AVDD) and ground (AGND) lines. AVDD=1.5 V-ΔV d, AGND=ΔV d w/o voltage drop compensationwith voltage drop compensation ΔV D =60 mV ΔV D =40 mV ΔV D =20 mV ΔV D =0 mV ΔV D =20 mV ΔV D =40 mV ΔV D =60 mV

13. FEE 2011- Bergamo, 23-27 May 2011 Effects on peaking time and charge sensitivity Voltage drop is simulated as a symmetrical voltage variation in the analog power (AVDD) and ground (AGND) lines. AVDD=1.5 V-ΔV d, AGND=ΔV d Charge sensitivity variation [%]Peaking time variation [ns]

14. FEE 2011- Bergamo, 23-27 May 2011 Apsel VI performance Apsel VI Charge sensitivity850 mV/fC Peaking time320 ns ENC34 e- Threshold dispersion before/after correction103/13 e- INL (@ 2000 e-)2.1% Analog power consumption33 μW/pixel Detector parasitic capacitance 300 fF Implemented structure128x100 pixels Pixel pitch50 μm

15. FEE 2011- Bergamo, 23-27 May 2011 Superpix1 3D hybrid chip front-end architecture Lower power consumption (I cell ≈ 7 μA) reduces the voltage drop effects on the channel-to-channel baseline voltage (V bl ) dispersion current mirror, also less noisy than transconductor. TIER1 (bottom) TIER2 (top) C 2 linearly discharged by a constant current I mir linear increase of the recovery time with input signal amplitude. Lower detector parasitic capacitance (C D ≈150 fF): lower noise and power consumption Fine tuning system in order to reduce the threshold dispersion: I DAC is set by a 4 bit current steering DAC in each channel. DAC driven by a thermometric code decoder. All in a 50 μm pixel pitch

16. FEE 2011- Bergamo, 23-27 May 2011 Superpix1 analog front-end Superpix1 Charge sensitivity48 mV/fC Peaking time @ 16000 injected electrons 260 ns ENC130 e- Threshold dispersion before/after correction 560/65 e- Analog power consumption10 μW/pixel Detector parasitic capacitance150 fF Implemented structure128x32 pixels Pixel pitch50 μm Main features This plot shows that an optimum condition exists for the threshold correction operation (DAC output range ≈ 5σ th ):

17. FEE 2011- Bergamo, 23-27 May 2011 Two different approaches are being considered for the design of the readout chip in view of applications to the SVT Layer0 of the SuberB factory. Conclusion and future plans Future steps include the characterization of both the chips (2011-12). Apsel VI and Superpix1 will be fabricated in the Globalfoundries-Tezzaron 130 nm 3D CMOS technology (to be submitted Q4 2011). MAPS and hybrid pixels can capitalize on 3D CMOS processes in terms of: immunity of the analog section (and of the sensor in MAPS) from digital signals increase of the functional density in the pixel cell higher collection efficiency (MAPS)