1. Compiler Research How I spent my last 22 summer vacations Philip Sweany

2. Why YOU should study compilers Combines “all” of computer science –Algorithms –Architecture –Software design, implementation, testing Useful in many computing disciplines –Architecture –Embedded applications –Natural language processing –Networks Fun

3. “Modern” Computer Systems Traditional “Systems” could be compiler OR operating systems MUCH more integrated now Include architecture, compiler, runtime support, OS, network Embedded Systems

4. Compiler/Architecture Generations 1945-1970, Dark ages 1970s, CISC era, find the “best” instruction 1980s, RISC era, cache improvement 1990s, Instruction-Level Parallelism (ILP), scheduling and register assignment 2000s, Thread-level parallelism, identify threads 2010s, Multi-core ?

5. Current Research Directions Refine techniques for “current” ILP computers (e.g. TI 6000 series) Investigate compiler issues for new types of architectures –Multithreaded –Hybrid –Dataflow

6. Multithreaded Fisher and Rau (1991) conjecture about best method to use available ILP Dataflow? Scheduled Dataflow (SDF) –Light-weight threads –Separate load/store (SP) from execution (EP) –Shows promise of scaling well

7. Hybrid Architectures Heterogeneous processors on single chip –“CPU” and FPGA –“CPU” and ASIC –N “CPU”s, M FPGAs, K ASICs Performance vs. power requirements Partition work among chip resources

8. Voltage-Frequency Regulator CPU 1 CPU 2 CPU m Multi-CPU FPGA 1 FPGA 2 FPGA n Multi-FPGA Shared Memory Power Supply Clocking Unit (V min, V max ) (f min, f max ) V1V1 V2V2 VmVm f1f1 f2f2 fmfm

9. System Specification Partitioning CPU Compiler FPGA Compiler CPU Power-Performance Model FPGA Power-Performance Model Source Code

10. Project Status Building on top of Scale compiler SDF compiler (from Scale) well underway Hybrid compiler in “pre-design” stage

11. More Specific Research Topics Thread identification in imperative code Support dataflow parallelism in loops CISC identification Partition code between CPU and FPGA resources (hardware/software co-design) Function reuse Memory system optimizations –Hardware malloc/free –Cache reconfiguration –Scratchpad memory

12. Want to Join ? Join Systems research group – meetings Friday at 10am in F219 Take CSCE 5400 (for parsing) Take CSCE 5650 (in Spring 08)