1. Technical University Tallinn, ESTONIA Overview: Fault Simulation Overview about methods Low (gate) level methods Parallel fault simulation Deductive fault simulation –Gate-level fault lists propagation (library based) –Boolean full differential based (general approach) –SSBDD based (tradeoff possibility) Critical path tracing Parallel critical path tracing Hierarchical fault simulation

2. Technical University Tallinn, ESTONIA Testide analüüs Rikete simuleerimise eesmärgid: -Arvutada rikete kate (testi kvaliteet) -Konstrueerida rikete tabel või sõnastik Rike Test Diagnostika sõnastik Testi analüüs – rikete simuleerimine Digitaal- süsteem Stiimul Reaktsioon

3. Technical University Tallinn, ESTONIA Faults in Digital Circuits 0110 T 6 0010011 FaultF 5 located Fault table Test experiment Test generation Fault simulation Fault diagnosis Fault modeling Testing How many rows and columns should be in the Fault Table?

4. Technical University Tallinn, ESTONIA Fault simulation Goals: Evaluation (grading) of a test T (fault coverage) Guiding the test generation process Constructing fault tables (dictionaries) Fault diagnosis Generate initial T Evaluate T Sufficient fault coverage? Modify T Done YesNo Random test generation Select target fault Generate test for target Fault simulate Discard detected faults Done No more faults Deterministic test generation

5. Technical University Tallinn, ESTONIA Defect and Fault Propagation An instance of an incorrect operation of the system being tested is referred to as an error The causes of the observed errors may be design errors or physical faults (defects) Physical defects do not allow a direct mathematical treatment of testing and diagnosis The solution is to deal with logical fault models System Component Defect simulation Error Fault simulation Defects, faults and errors

6. Technical University Tallinn, ESTONIA Fault simulation Fault simulation techniques: serial fault simulation parallel fault simulation deductive fault simulation concurrent fault simulation critical path analysis parallel critical path analysis Common concepts: fault specification (fault collaps) fault insertion fault effect propagation fault discarding (dropping) Comparison of methods: Fault table Faults F i Test patterns T j Entry (i,j) = 1(0) if F i is detectable (not detectable) by T j

7. Technical University Tallinn, ESTONIA Single and Parallel SAF Fault Simulation Fault-free circuit: Faulty circuit: & 1 x1x1 x2x2 x3x3 z y 0 1 0 0 0 & 1 x1x1 x2x2 x3x3 z y 0 1 1 0 1 Inserted stuck-at-1 fault Detected error Parallel patterns Fault-free circuit: Faulty circuit: & 1 x1x1 x2x2 x3x3 z y 001 101 001 010 011 & 1 x1x1 x2x2 x3x3 z y 001 101 111 010 111 Inserted stuck-at-1 fault Detected error Three test patterns Single pattern

8. Technical University Tallinn, ESTONIA Parallel Fault & Test Pattern Simulation Parallel patterns Fault-free circuit: Faulty circuit: & 1 x1x1 x2x2 x3x3 z y 001 101 001 010 011 & 1 x1x1 x2x2 x3x3 z y 001 101 111 010 111 Inserted stuck-at-1 fault Detected error Parallel faults & 1 x1x1 x2x2 x3x3 z y 000 111 0 1 0 000 010 Stuck-at-0 Stuck-at-1 Computer word Fault-free Detected error Inserted faults Three test patterns

9. Technical University Tallinn, ESTONIA Deductive Fault Simulation & & 1 1 1 2 3 4 5 a c b 1 1 0 0 0 0 0 1 1 y Fault list calculation: L a = L 4  L 5 L b = L 1  L 2 L c = L 3  L a L y = L b - L c ----------------------------------------------------------- L y = ( L 1  L 2 ) - (L 3  (L 4  L 5 )) Gate-level fault list propagation L a – faults causing erroneous signal on the node a L y – faults causing erroneous signal on the output node y L1L1 L2L2 L3L3 L4L4 L5L5 Library of formulas for gates

10. Technical University Tallinn, ESTONIA Boolean derivatives Boolean function: Y = F(x) = F(x 1, x 2, …, x n ) Boolean partial derivative:

11. Technical University Tallinn, ESTONIA Boolean differentials dx - fault variable, dx  (0,1) dx = 1 - if the value of x has changed because of a fault Partial Boolean differential: Full Boolean differential:

12. Technical University Tallinn, ESTONIA Fault Simulation with Boolean Differentials & x1x1 x2x2 y 1 0 0 {x 2  1} {x 2  1, y  1} & x1x1 x2x2 y 1 1 1 {x 1  0} {x 2  0} {x 1  0, x 2  0, y  0} 1 x1x1 x2x2 y 1 0 1 {x 1  0} {x 2  1} {x 1  0, y  0}

13. Technical University Tallinn, ESTONIA Deductive Fault Simulation with BDs & & 1 1 1 2 3 4 5 a c b 1 1 0 0 0 0 0 1 1 y Fault list calculated: L y = ( L 1  L 2 ) - (L 3  (L 4  L 5 )) Macro-level fault propagation: Solving Boolean differential equation:  L k A B AB A B

14. Technical University Tallinn, ESTONIA Critical Path Tracing & & 1 1 1 2 3 4 5 a c b 1 1 0 0 0 0 0 1 1 y 12 34 5 y Problems : & & 1 1 1 1/01/0 y 1/0 1 1 The critical path is not continuous & & 1 0 1 1 y 1/0 1 1 The critical path breaks on the fan-out

15. Technical University Tallinn, ESTONIA Fault Simulation with Boolean Derivatives & 1 x1x1 y 1011 1110 1001 1011 Detected faults vector: - 10 - T1: No faults detected T2: x 1  1 detected T3: x 1  0 detected T4: No faults detected x3x3 x2x2 Simulation approaches: 1)Single fault simulation 2)Parallel fault simulation for a subset of test patterns (by extending bit-operations to operations with computer words) 3)Iterative fault simulation for subsets of faults (by creating transitive closures – deductive simulation and critical path tracing) 4)Parallel fault reasoning for both, patterns and faults

16. Technical University Tallinn, ESTONIA Parallel Critical Path Tracing & 1 x1x1 y 1011 1110 1001 1011 Detected faults vector: - 10 - T1: No faults detected T2: x 1  1 detected T3: x 1  0 detected T4: No faults detected x3x3 x2x2 Handling of fanout points: Fault simulation Boolean differential calculus x y xkxk x2x2 x1x1 F

17. Technical University Tallinn, ESTONIA Parallel Critical Path Tracing Handling of fan-out points in a single tree in general case: x y xkxk x2x2 x1x1 F x k+1 xnxn x x 1,h x 1,h-1 x 1,2 x 1,1 x1x1 All the Boolean operations can be carried out in parallel

18. Technical University Tallinn, ESTONIA Parallel Critical Path Tracing Problem with fan-out points:

19. Technical University Tallinn, ESTONIA 1) R 1P – set of faults found by parallel critical path tracing R* = R’ 1P - R 1P - set of faults found by critical path tracing, which propagate to the next cycle R 1P R 1P ’ Time Calculation of detected faults by combining single and parallel fault simulation 2) R 2P – R* + R 2S R* = R’ 2P + R’ 2S – R 2P R 1P R 1P ’ R 2P – parallel simulation R 2S - single fault simulation R 2S R’ 2S R’ 2P – parallel simulation R’ 2S - single fault simulation Fault Simulation in Sequential Circuits

20. Technical University Tallinn, ESTONIA Parallel Sequential Critical Path Tracing Design for Testability based on using Signature Analyzers (SR): SR can be connected to the “problem causing” test points The fault will be captured at the first occasion. The detection of the fault will be fixed, and we can ignore its impact in the future

21. Technical University Tallinn, ESTONIA Non-primitive polynomial x 4 + x 2 + 1 LFSR – Linear Feedback Shift Register xx2x2 x3x3 x4x4 0001 1000 0100 1010 0101 0010 0001 1001 1100 1110 1111 0111 0011 1001 0110 1011 1101 0110 Primitive polynomial x 4 + x + 1 xx2x2 x3x3 x4x4 0001 1000 1100 1110 1111 0111 1011 0101 1010 1101 0110 0011 1001 0100 0010 0001

22. Technical University Tallinn, ESTONIA Pseudorandom Test with LFSR LFSR – Linear Feedback Shift Register: Polynomial: P(x) = x 4 + x 3 + 1 x3x3 x2x2 x4x4 x Two functions: test generation and signature analysis UUT Test patterns Test responses

23. Research in ATI © Raimund Ubar Algorithm: 1.Determine the activated path to find the fault candidates 2.Analyze the detectability of the each candidate fault (each node represents a subset of real faults) Fault Analysis with SSBDDs x11x11 y x21x21 x12x12 x31x31 x4x4 x13x13 x22x22 x32x32 0 1 0 1 23 & & & 1 & x1x1 x2x2 x3x3 x4x4 y x11x11 x 21 x12x12 x 31 x13x13 x 22 x 32 0 1 0 0 0 1 0 0

24. Research in ATI © Raimund Ubar 24 Properties of SSBDDs Property 1: If a b ), and no 1-path (0-path) can be activated from b, then also no 1-path (0-path) from a can not be activated b a Y The task is to find a solution for Y = 1 The nodes in SSBDD are ordered: if a < b, then there is no path from b to a Test pattern generation can be speed-up using Property 1

25. Research in ATI © Raimund Ubar 25 Optimized Critical Path Tracing with BDDs Property 2: If a test vector X activates in SSBDD a 0-path (1-path) which travers a subset of nodes M, then only 0-nodes (1-nodes) have to be considered as fault candidates Speeding-up simulation: M = {1,2,3,4,6,7} M* = {1,6,7} – by Property 2 M** = {6,7} – by Property 1 Fault diagnosis and fault simulation can be speed-up by using Property 2 Only 6 and 7 have to be considered Fault diagnosis / Fault simulation: y y

26. Research in ATI © Raimund Ubar 26 Parallel Fault Simulation with SSBDDs m var x(m)D(m)L(m)S(y,x(m)) 1 X1X1 1001110011111010 2 x2x2 11101001 3 x3x3 0101010001110100 4 x4x4 01010001 5 x5x5 0100 0001 6x6x6 0000 0011 We start from the node with the highest label m =6, and repeat for each node the vector operation (m 0 and m 1 are the neighbours of m to 0-direction and 1-direction, respectively): The result of simulation D(m) will be the value of y calculated for the root node m = 1 Parallel fault free simulation For m =6, D(m 1 ) = 11...1 and D(m 0 ) = 00...0 D(m) – the value of the function at the node m

27. Research in ATI © Raimund Ubar Parallel Fault Simulation with SSBDDs m var x(m)D(m)L(m)S(y,x(m)) 1 X1X1 1001110011111010 2 x2x2 11101001 3 x3x3 0101010001110100 4 x4x4 01010001 5 x5x5 0100 0001 6x6x6 0000 0011 Calculation of candidates of detected faults For each test pattern, the nodes m are found where L(m) = 1 by iterative calculation: The initial values are: L(m 0 ) = 11...1 and for all other nodes m i L(m i ) = 00...0. The value of the vector component L k (m)=1 means that the node m was traversed by the test pattern

28. Research in ATI © Raimund Ubar 28 Parallel Fault Simulation with SSBDDs m var x(m)D(m)L(m)S(y,x(m)) 1 X1X1 1001110011111010 2 x2x2 11101001 3 x3x3 0101010001110100 4 x4x4 01010001 5 x5x5 0100 0001 6x6x6 0000 0011 We find at which nodes of activated paths the faults are detected. Detectability S(y,x(m)) of faults at x(m) observable at y is calculated in parallel for a bunch of test patterns: The simulation procedure consists of two runs: 1)For D(m) starting from the last node, and 2)For L(m) and S(m) starting from the root node Parallel critical path tracing:

29. Research in ATI © Raimund Ubar Logic Simulation Along Hamiltonian Path Network of 3 sub-circuits: y1y1 x1x1 x2x2 x3x3 x4x4 x5x5 x6x6 x7x7 x8x8 FFR y2y2 x3x3 x 3 x 5 x 4 x 6 x 8 x 7 x 1 x 2 x 4 x 5 y2y2 y1y1 x 1 x 2 x 5 x 1 S 3 BDD Connected full Hamiltonian path for the S3BDD model: x 8 x 7 x 6 x 5 x 4 x 2 x 1 Simulation flow x3x3 y2y2 y1y1 Simulation start Calculated intermediate values Simulation trace can be carried out in parallel for many patterns

30. Technical University Tallinn, ESTONIA Defect 01010101 Defect is detected Fault model versions: Conditional fault Pattern fault Constrained SAF Cell aware test SAF 1 1 01010 1 0 n.. t t-1 … 0 Simulation table Test pattern number Detected SAF Transition fault not detected Transition fault detected Lines in the circuit 1 1 1 Bridging fault detected Transition fault not detected Simulation of Diferent Classes of Faults

31. Technical University Tallinn, ESTONIA Hierarchical Concurrent Fault Simulation High-Level component High-Level component High-Level component Sequence of patterns P: First Pattern R: Faults Set of patterns With faults P;P 1 (R 1 )…P n ( R n ) Set of patterns with faults P;P 1 (R 1 )…P m ( R m ) P: Pattern Set of patterns with faults P;P 1 (R 1 )…P n ( R n )

32. Technical University Tallinn, ESTONIA Hierarchical fault simulation Main ideas of the procedure: A target block is chosen This will be represented on gate level Fault simulation is carried out on the low level The faults through other blocks are propagated on the high level

33. Technical University Tallinn, ESTONIA Hierarchical fault simulation

34. Technical University Tallinn, ESTONIA Hierarchical fault simulation Definition of the complex pattern: D = {P, (P 1,R 1 ), …, (P k, R k )} P is the fault-free pattern (value) P i (i = 1,2,..., k) are faulty patterns, caused by a set of faults R i All the faults simulated causing the same faulty pattern P i are put together in one group R i R 1 - R k are the propagated fault groups, causing, correspondingly, the faulty patterns P 1 - P k

35. Technical University Tallinn, ESTONIA Fault Simulation with DD-s Fault propagation through a complex RT-level component q xAxA xcxc B C A D q = {1, 0 (1,2,5), 4 (3,4)}, D xA = {0, 1 (3,5)}, D xC = {1, 0 (4,6)}, D A = {7, 3 (4,5,7), 4 (1,3,9), 8 (2,8)}, D B = {8, 3 (4,5), 4 (3,7), 6 (2,8)}, D C = {4, 1 (1,3,4), 2 (2,6), 5 (6,7)}. Decision diagram New D A to be calculated Sub-system for A A 0 1 0 q xAxA B + C A + 1 13 xCxC A + C 04 xAxA A 0 xCxC 2 1 0 A - 1 A + B

36. Technical University Tallinn, ESTONIA Fault Simulation with DD-s Example of high level fault simulation D q = {1, 0 (1,2,5), 4 (3,4)}, D xA = {0, 1 (3,5)}, D xC = {1, 0 (4,6)}, D A = {7, 3 (4,5,7), 4 (1,3,9), 8 (2,8)}, D B = {8, 3 (4,5), 4 (3,7), 6 (2,8)}, D C = {4, 1 (1,3,4), 2 (2,6), 5 (6,7)} Final complex vector for A: D A = {8, 3(4), 4(3,7), 5(9), 7(5), 9(1,8)}

37. Technical University Tallinn, ESTONIA Parallel Critical Path Tracing Handling of fan-out points in a network of nested trees: FyFy d y e D Ez c b C q A x B FzFz XyXy XzXz. where Two fanouts: q, x A,B,D,E – chains of Boolean derivatives All calculations can be carried out in parallel

38. Technical University Tallinn, ESTONIA Fault Simulation in Sequential Circuits Critical path tracing: F1F1 R6R6 R1R1 R2R2 R7R7 X1X1 X2X2 X3X3 F2F2 F3F3 F4F4 R8R8 R4R4 R5R5 R3R3 X4X4 F5F5 F7F7 F8F8 F6F6 R 10 X5X5 R9R9 Y2 Y1 Z1Z1 Z2Z2