1. POWER OPTIMIZATION IN RANDOM PATTERN GENERATOR By D.Girish Kumar 108W1D8007

2. CONTENTS: Abstract Introduction Conventional LFSR Bit Swapping LFSR Simulation Results Advantages Applications Conclusion References

3. ABSTRACT Generally LFSR are high correlations are between the consecutive patterns are higher in testing mode it leads to optimize more power. So, the proposed Bit Swapping LFSR for test-per-scan BIST is based upon some new observations concerning the number of transitions produced at the output of an LFSR.

4. INTRODUCTION Now a days all the demand for portable computing devices and communications system is increased rapidly. The operational speed of those devices are very high and output is susceptible to environmental conditions. So, every device is need to check while it is running for each and every pattern.

5. MOTIVATION During testing mode several methods are proposed to optimize the power but it simultaneously increases the device cost so Bit-Swapping LFSR is proposed with two goals: Reduce the number of transitions in randomly generated patterns. Reduce the number of specified bits by generating LFSR seeding.

6. CONVENTIONAL LFSR

7. TEST PATTERNS 0101 1011 0111 1111 1110 1100 1000 0001 0010 0100 1001 0011 0110 1101 1010 0101

8. BIT-SWAPPING LFSR

9. COMPARISION FOR CONVENTIONAL LFSR AND BIT SWAPPING LFSR: GENERAL LFSRBIT SWAPPING LFSR0110 11011011 1010 0101 1011

10. SIMULATION RESULT FOR CONVENTIONAL LFSR:

11. SIMULATION RESULT FOR BIT-SWAPPING LFSR:

12. ADVANTAGES Low power. Less complexity. Low cost. Easy to use in any type of applications. Fault coverage is negligible.

13. APPLICATIONS Counters. Digital Broadcasting and Communication. Built-in self Test. Code Division Multiple Access. Pattern Generators.

14. CONCLUSION A low transition test pattern generator, called Bit Swapping LFSR is designed to reduce average and peak power of a circuit during test by reducing the transitions within test pattern and between consecutive patterns.

15. REFERENCES Mr.Balwinder Singh,Mr.Arun Khosla and Mr.Sukhleen Bindra“Power optimization of Linear Feedback Shift Register (LFSR) for low power BIST” 2009, IEEE International Advance Computing Conference (IACC 2009). Mr. Gregor Papa, Mr.Franc Novak “Deterministic test pattern generator design with genetic algorithm approach “Journal of Electrical Engineering,Vol.58,No.3,2007,121-127. Mr.V.Ramesh “Test power Comparison in BIST” International Jouranl of Advanced Science and Engineering Technologies,Vol.7,Issue 2.