1. DHH Status Igor Konorov TUM, Physics Department, E18 PXD DAQ workshop Münzenberg –June 9-10, 2011

2. Pending issue of DHH interfaces PXD DAQ Workshop Münzenger И.Коноров, TUM FTSW PXD DAQ DHH Controller DHH GCK, FCK TRG, RST DHP DATA(3:0) Timing JTAG DATA(3:0) Timing JTAG Copper Optical

3. With or WO DHH Controller Agreed to develop prototype compatible with both solutions Prototype module can perform both functions DHH and DHH controller Proposal : No discussion of two options till prototype test completion PXD DAQ Workshop Münzenger И.Коноров, TUM

4. Foreseen interfaces DHP –2xInfiniband connector (16 differential lines) DAQ –2xSFP+ serial links 6.5 Gb/s, compatible with new IHEP AMC card DHH Controller –SFP+ serial link FTSW –RJ45 Timing interface –RJ45 JTAG interface DDR2 SODIMM –Clustering ASIC –Data buffer Lab setup –RJ45 Ethernet Extra connectors for existing DHP setup –SMA connectors –LVDS signals PXD DAQ Workshop Münzenger И.Коноров, TUM

5. Hardware features 6U VME standard XC6VLX75T-FF784 Xilinx FPGA Flash memory for two firmware versions –Golden version – stable, minimum functionality, loaded after power up –Working version – loaded after initialization Up to 2GByte DDR2 memory I/O isolation DC/DC converter up to 1500 V Clock divider and jitter cleaner Si5322 PXD DAQ Workshop Münzenger И.Коноров, TUM

6. DHH functions Clock synthesis –3/20 of 508.89 MHz RF clock = 76.33 MHz Data handling –Data buffering –Reformatting data from Frame ordered to Event ordered –Merging four DHP data streams into two DHH streams JTAG support –FPGA and flash memory programming –DHP, DCD configuration parameters PXD DAQ Workshop Münzenger И.Коноров, TUM

7. New DHP data format PXD DAQ Workshop Münzenger И.Коноров, TUM

8. Data handling Step 1: Data Reformatting –DHP: … –DHH: … Event M-1 > Event M > … Step 2: Data Merging –Event M-1 –Event M Data reformatting increases data rate by 25 % PXD DAQ Workshop Münzenger И.Коноров, TUM

9. JTAG interfaces DHH  DHP LVDS standard powered by 2.5V @DHH and 1.5V @ DHP TCK frequency up to 10 MHz Loading configuration information Synchronous JTAG commands with bunch injection Read full frame during bunch injection Changing DHP readout mode from zero suppression to full readout and back Updating pedestals every few seconds DHH FPGA Updating firmware Reading status information PXD DAQ Workshop Münzenger И.Коноров, TUM

10. JTAG slow control architecture Possible architectures: 1.Linux PC  CN Power PC  DHH 2.Linux PC  FTSW  DHH 3.Linux PC  DHH Controller(MicroBlaze)  DHH 4.Linux PC  FTSW  DHH controller  DHH 5.… Slow control system strongly depends on DHP features Good news: Sergei started to look at this issues PXD DAQ Workshop Münzenger И.Коноров, TUM

11. DHH status PXD DAQ Workshop Münzenger И.Коноров, TUM Done Synchronous clock distribution with Xilinx FPGA Clock synthesis DHP interface mechanics and electrical specifications Work in progress Schematic in progress New requirements have been implemented : SODIMM Interface to DHP agreed with Bonn Interface to current monitor to be defined Plans Work on slow control system aspects with Slow Control expert Finalize schematic and verify with Bonn Start production in end of June

12. SPARE SLIDES PXD DAQ Workshop Münzenger И.Коноров, TUM

13. DHP – DHH interface To DHP –GCK (LVDS/2.5V) – 3/20 of 508.89 MHz = 76.33 MHz –FCK (LVDS/2.5V) – Frame clock about 50 kHz –TRG (LVDS/2.5V) –RST (LVDS/2.5V) –JTAG differential interface TCK, TDI, TDO, TMS From DHP –DATA (0 : 3) @ 1.6 Gb/s –CDC current monitor PXD DAQ Workshop Münzenger И.Коноров, TUM

14. Test setup DEPFET workshop, Bonn И.Коноров, TUM 14 TX SYNC PULSE RX SYNC PULSE

15. RX Clock phase scan DEPFET workshop, Bonn И.Коноров, TUM 15 Clock phases after applying multiple RX reset

16. Deserializer synchronization circuit RX0 – time reference RX RX1 – being synchronized RX Synchronization procedure 1.Reset RX1 until maximum clock phase difference detected 2.Reset RX1 until one predefined(earliest) clock phase detected DEPFET workshop, Bonn И.Коноров, TUM 16 RX0 RX1 Phase alignment logic FPGA RX RESET

17. Link synchronization Synchronization procedure 1.Synchronize TX 2.Synchronize RX1 Status : –VHDL code developed and tested DEPFET workshop, Bonn И.Коноров, TUM 17 RX0 RX1 Phase alignment logic FPGA RX RESET TX RX Phase alignment logic FPGA RX RESET TX RESET