1. KIT – University of the State of Baden-Wuerttemberg and National Research Center of the Helmholtz Association Institute for Data Processing and Electronics www.kit.edu Detector Technology and Systems Platform S2: Ultrafast Communication and Analysis Andreas Kopmann

2. Institute for Data Processing and Electronics 29. Mai 2012 Applications at KIT Research field: Structure of Matter Astroparticle physics: Auger / FD, Radio detector Neutrino physics KATRIN Dark matter: Edelweiss High energy physics Operation of the light source ANKA HDRI Ultrafast tomography / GPU Computing Querschnitt: Ultrasound computer tomography Early breast cancer diagnostics Workshop on Ultrafast Communication and Analysis

3. Institute for Data Processing and Electronics 39. Mai 2012 Applications at KIT Workshop on Ultrafast Communication and Analysis Structure of Matter „Querschnitt“ Neutrino Experiment KATRIN Astroparticle Physics Pierre Auger Observatory Ultrasound Computer Tomography Early breast cancer diagnostics High-engery Physics KIT Light Source ANKA High Data Rate Processing and Analysis Initiative HDRI

4. Institute for Data Processing and Electronics 49. Mai 2012 High Speed Optical Communication Technology Workshop on Ultrafast Communication and Analysis Optical modulation: Higher speeds possible than with directly modulated laser diodes Power efficient Mach-Zehnder modulator phase modulator phase modulator (optional) splitter combiner constructive or destructive interference cw laser detector Encoding information on light at 42 Gbit/s (the first electro-optic silicon modulator) 1 pJ/bit power consumption with potential go down to 10 fJ/bit1 pJ/bit power consumption with potential go down to 10 fJ/bit C. Koos et al., Nature photonics 3, 216-219 (2009) Work package 7: Goal: Monolithic Photonic Integrated Circuits Goal: Monolithic Photonic Integrated Circuits

5. Institute for Data Processing and Electronics 59. Mai 2012 High-throughput Camera Platform Workshop on Ultrafast Communication and Analysis Prototype Readout board (Xilinx ml605) Daughter board with CMOSIS sensor External PCI Express Link (to compute server) The main features: PCI Express interface for continuous data acquisition at full speed (ca. 2 GB/sec) Easily extendable to any available CMOS image sensor Fully programmable  adjustable image exposure time and dynamic range, analog and digital pixel features as pixel threshold, mask, analog gain, on-line image processing etc. Xilinx FPGA (for fast readout & on-line data process) Large DDR3 local memory Work package 6:

6. Institute for Data Processing and Electronics 69. Mai 2012 Standardization: xTCA for Physics Workshop on Ultrafast Communication and Analysis HW Development at DESY xTCA.4 compatible board Based on DAMC2 module Similar functionality Lower Price and/or higher performance New generation of FPGAs First Kintex7 and later Zynq 28 nm low power technology Up to 16 12.5 Gb/s transceivers DDR3 memory Up to 350000 Logic Cells Up to 500 I/Os ARM or soft-core processor Firmware Development at KIT AXI4 (ARM AMBA 4.0) Bus Architecture High Performance Memory mapped Low Throughput High speed streaming User-Framework with ready to use modules for board peripherals Memory Interface Rear Transition Module PCIe Interface FMC Interface Linux OS Integration

7. Institute for Data Processing and Electronics 79. Mai 2012 Verbesserung der Einsetzbarkeit FPGA basierter Systeme bei hoher Strahlenbelastung Internal KIT Funding Entwurf, Aufbau und Betrieb einer Meßeinrichtung am Zyklotron. Erste Beurteilung der Strahlenempfindlichkeit von FPGAs Erste Bewertung der Gegenmaßnahmen, wie Sie in der Literatur für ähnliche Anwendungsbereiche (z.B. Weltraumanwendungen) beschrieben werden. Workshop on Ultrafast Communication and Analysis

8. Institute for Data Processing and Electronics 89. Mai 2012Workshop on Ultrafast Communication and Analysis Young Investigator Group CADEMA: Computer Aided Design and Exploration of Multi-Core Architectures Research Objective Development of novel methods and tools to support application developers with: Selecting a heterogeneous multi-core architecture which fulfills the constraints of the target application Efficient application parallelization for the target multi-core architecture Research Objective Development of novel methods and tools to support application developers with: Selecting a heterogeneous multi-core architecture which fulfills the constraints of the target application Efficient application parallelization for the target multi-core architecture

9. Institute for Data Processing and Electronics 99. Mai 2012 GPU Computing: Tomographic Reconstruction Workshop on Ultrafast Communication and Analysis Sample:Plastic holder with porose polyethylene grains Source data:24GB (2000 projections, 3 Mpix @ 32 bits) 3D Image: 11GB (3 Gtexel @ 32 bits) Complexity: 54 Tflop computation complexity 77x - Reconstruction 45x – I/O (storage) 57x - Overall 3D reconstructed sampleSingle projection Used as test bench I/O (storage) GPU server commissioned in ANKA Work package 8:

10. Institute for Data Processing and Electronics 109. Mai 2012 Optimization for Graphic Processors (GPUs) Workshop on Ultrafast Communication and Analysis

11. Institute for Data Processing and Electronics 119. Mai 2012 GPU Computing for Scientific Applications Workshop on Ultrafast Communication and Analysis

12. Institute for Data Processing and Electronics 129. Mai 2012 Summary Work package 7: Optical Communications Research on optical modulation Monolithic Photonic Integrated Circuit Work package 6: Intelligent Logic High-throughput Camera Platform Standardization: xTCA Effects of Radiation on FPGAs Computer Aided Design and Exploration of Multi-Core Architectures Work package 8: GPUs for Scientific Applications Parallel Computing Framework Workshop on Ultrafast Communication and Analysis