2. Beam Secondary Shower Acquisition System for Wire Scanners using Diamond Detectors BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 2 Jose Luis Sirvent Blasco (BE/BI-BL) PhD. Student DI Day Centre de Conventions - Archamps 16/10/2014

3. Outline 1. Introduction Current System & Limitations Upgrade on the Secondary Particle Acquisition Why Diamond Detectors? 2. Studying Possibilities Long Coax VS Optical Link CK50 Cable Characterization / Simulations 3. Proposed Architecture 4. GBT Implementation on Igloo2 5. Electronics Development Readout ASICs Prototype Boards Development 6. Summary & Plans BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 3

4. 1. Introduction 1.1 Current system Invasive method for beam transverse profile measurement. Carbon wire interaction (30um) generates shower of secondary particles. Transversal profile: Wire position (X axis) Secondary rain (Y axis) System compromises: Wire blow-up (heat) Losses produced Mechanical stresses (Bellows) Calibration procedures Vibrations Types: Rotating Fast Rotating Short/Long Linear Total Scanners @ CERN: 31 4

5. 1. Introduction 1.1 Current system (limitations) Better reproducibility & accuracy needed for scans: Beam size min LHC 130 um, PSB 2000 um Sensors and actuators outside vacuum chamber: Not direct measurement of wire position (External potentiometer) Not direct relationship motor/wire movement (Mechanical transformations) Mechanical play Secondary Particle acquisition system: Need to Set-up working point of PMT (Amplif.) & Filters (Which) Working point has a clear impact in the Beam sigma measurement (PMT Saturation) Limited dynamic range in any configuration (Tails measurements) High Intensity beams rise up the noise level and therefore decreases the dynamic range. Aging of bellows: Limits the operational life of the BWS In case of an accident the Vacuum is lost Many different mechanics: Wire Scanners dedicated to Accelerators Scintillator Filters PMT Preamplifiers (**)Acquisition system and PMT saturation effect 5

6. Motivation: Improvements with respect to previous system (obviously) Usage of a new detector, pCVD diamond detector. Acquisition system with high dynamic range without tuneable parameters. Low noise measurements for Gaussian tails / halo measurements. A single system for all accelerators LHC, SPS, PS & PSB. Bunch by Bunch Synchronous measurements (profiles) 1. Introduction 1.2 Upgrade on the Secondary Particle Acquisition Carbon Wire 6

7. Proposed detector for secondary particles: pCVD diamond detector This is a Solid State Ionization Chamber: Energy deposited  Generation mobile charges e-h  Electrical current when applying Vbias Already validated for Single particle detection (*) as well as for Intense beams (**) Linearity already proven in very large dynamic ranges, from few  A for MIP’s to Amps. Many Know-How at CERN, RD42 collaboration, and already used in BE/BI-BL, Atlas BCM, CMS BCM… (*) B.Dehning, E. Effinger, H. Pernegger, D. Dobos, H. Frais-Kolbl, E.Griesmayer. Test of a Diamond Detector using Unbunched Beam Halo Particles. Feb.2010 (**) J.L. Fernandez-Hernando. Development of a Beam Condition Monitor system for the Experimental Areas of the LHC using CVD Diamond. PhD. Thesis (***) C.Kurfuerst et al. “Radiation Tolerance of Cryogenic Beam Loss Monitor Detectors. 4th International Particle Accelerator Conference”, Shanghai, China, 12 - 17 May 2013 Copyright©: CIVIDEC Instrumentation GmbH 1. Introduction 1.3 Why Diamond Detectors? 7 (****)PropertySiDiamondAdvantage Band gap [eV]1.125.45 Low I leakage e- mobility [cm2/Vs]14502200 Faster Signal (Better temporal resolution) H mobility [cm2/Vs]5001600 Dielectric constant11.95.7Low Capacitance/noise Displacement E [eV]13-2043High Rad-hardness Ionization Energy for e-h[eV]3.613 Smaller signal Av. E-h per MIP per mm8936 Charge Coll. Eff [%] 10050 in pCVD 100 in sCVD Thermal conduct [W/cm K]1.522No cooling

8. 2. Studying Possibilities 2.1 Long Coax (Analog) VS Optical Link (Digital) Two different approaches considered at the beginning of the project: Analog Signal Transmission: Simple Front-End development to drive long CK50 lines. Effort on Back-End. Digital Signal Transmission: Development of Front-End modules (Rad-Hard development) First Project Stage (Decision making stage): Diamond Detector characterization  Electrical model, Solid state Ionization chambers understanding… Signal simulation and dynamic range needed  Signal estimations through calculations based on Fluka simulations. Long cable modelling and study of signal degradation  Validation of theoretical frequency response and simulations. BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 8 pCVD Diamond Detector Splitting System (PreAmplif) Digitalization (ADC,Integration) Storage and Processing Optical link Interface Optical link Interface pCVD Diamond Detector Splitting System (PreAmplif) Digitalization (ADC,Integration) Storage and Processing SurfaceTunnel Coaxial cables Fibre Optic

9. BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 9 2. Studying Possibilities 2.2 CK50 Cable characterization (Measurements) 1.Frequency Response: Aim: Extract Bode Plots for analytical model development & Validation 2.Temporal Response: Aim: Pulse degradation dispersion, temporal response. 3.Nose Pick-Up: Aim: Study possible sources for SNR degradation (TV & Radio stations, Ventilators, EM coupling…) Place: SPS BA5 on 07/2013 A cable model was developed and validated for simulations

10. BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 10 2. Studying Possibilities 2.3 CK50 Model Validation (Frequency Response)

11. 2. Studying Possibilities 2.3 CK50 Model Validation (Temporal Response with different pulses) BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 11 Input Signal Output Signal Model Output (Fitting ~ 85 - 95%)

12. BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 12 2. Studying Possibilities 2.4 Current system simulation PMT CK50 Coax 10m IBMS Board Bunch Integration Nominal LHC 25ns Bunch Sigma 1ns Bunch separation 25ns Different Emitances used in Odd & Even bunches  Two profiles used on simulation Evaluation of bunch dispersion on bunch sigma determination Short CK50 Cable (10m)  No signal degradation. Profiles as original Zoom Wire Scan Simulation

13. BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 13 2. Studying Possibilities 2.4 Current system simulation Zoom Different Emitances used in Odd & Even bunches  Two profiles used on simulation Evaluation of bunch dispersion on bunch sigma determination Long CK50 Cable (250m)  Bunch pile-up observed. Profiles affected by an offset. Nominal LHC 25ns Bunch Sigma 1ns Bunch separation 25ns PMT CK50 Coax 250m IBMS Board Bunch Integration Wire Scan Simulation

14. The bunch pile-up affects the measurement adding error on profiles. Longer cables  More pile-up & More error on sigma. BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 14 2. Studying Possibilities 2.4 Current system simulation (Impact on Bunch Sigma)

15. BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 15 2. Studying Possibilities 2.4 Current system simulation (Impact on Bunch Sigma) Sigma error not only depends on cable length, but also on sigma ratios. Consecutive bunches with big emitance differences  Bigger induced errors for the same cable length.

16. BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 16 2. Studying Possibilities 2.4 Current system simulation (Impact on Profiles) Gaussian Goodness-of-fit evaluation through SSE (Sum of Squares Due to Error) VS Cable Length (m) Bunch Sigma Error VS Cable Length(m) Sigma errors increase with length and sigma difference Gaussian fit quality decreases with distance and Sigma difference

17. BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 17 2. Studying Possibilities 2.4 Current system simulation (Impact on Profiles) Gaussian Goodness-of-fit evaluation through SSE (Sum of Squares Due to Error) VS Cable Length (m) Bunch Sigma Error VS Cable Length(m) Sigma errors increase with length and sigma difference Gaussian fit quality decreases with distance and Sigma difference In conclusion: There is profile cross-talk due to bunch overlapping. Needed to maintain bunch isolation for accurate bunch by bunch profiles. Needed to avoid long cabling for signal integrity reasons.

18. 2. Studying Possibilities 2.4 Noise Pick-Up BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 18 Main Contribution  330KHz Frequency Spectrum Noise Distribution Raw Signal Sigma  0.33mv Peak-Peak  1.25mV A limiting factor for Gaussian Tails measurements and Gaussian Fit quality. Found Noise in a critical Freq. Band (330KHz) Why not to high-pass filter? Fc ~ 400KHz Gaussian deformation Fc ~ 200MHz Mean bunch charge = 0fC Why not to Shape? Many different beam dynamics. DC coupling needed.

19. 3. Proposed Architecture 3.1 A Front-End / Back-End based approach BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 19 Usage of the GBT project for Data, Control and Timing transmission FE BE GBT Protocol @ 4.8Gbps Beam Synchronous measurements Two serious candidates as readout ASIC for pCVD diamond Detector: ICECAL (LHCb) QIE10 (CMS) We’ll design for tunnel radiation levels: 100Gy/year  up to 1KGy (10 years)

20. 4. GBT implementation on Igloo2 4.1 Why GBT-On-Igloo2? Our Base Solution would be GBTx ASIC: Not available at the initial developments. Needed a Back-Up Solution based on Emulation: Igloo2 was a promising candidate even for final system Flash Based FPGA with “SEU Immune” configuration memory New FPGA in 65nm technology, and first Flash-based that includes SERDES @ 5Gbps Positive experiences with previous family in other experiments ProASIC3. Potential collaborations. BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 20 FPGA Characteristics Technology Flash-Based Vendors Microsemi Families ProASIC3, SmartFussion, Igloo Configuration Tolerant to SEUs Yes Configuration SEU Mitigation Techniques TMR Typical TID Limits 20-40 kRad (ProASIC3) 100s kRad (maybe IG2)** Comments Reprogramming improves performance. **Still under characterization Adaptation of GBT_FPGA code Xilinx Virtex 6  Microsemi Igloo2

21. 4. GBT implementation on Igloo2 4.2 Tests Set-Up BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 21 The modified version of GBT_FPGA for Igloo2 was finally implemented correctly @ 5Gbps. The GBT Firmware was finally organized & commented properly, including an error counter and Boards auto-detection. The Console Application was developed for testing/debugging. Needed to verify timing details to check if we can recover the LHC clock on the front-end system. (Study the recovered Clk phase, link latency and ref frequency tolerance TX  RX).

22. 4. GBT implementation on Igloo2 4.6 Clock Recovery and Link Latency (41.6Mhz @ 5Gbps) BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 22 Measurements on LATOP Version: Clock Recovery (Frame_CLK 41.6Mhz): Essential for Bunch Synchronous Acquisitions Delay defined by BITSLIP_NUMBER compensated Use of PLL delay lines (steps of 100ps) 20 possible delays (0 - 1.34 ns) Stable Recovered Phase : ± 2.8% uncertainty Link Latency: The clocks alignment allows stable link latency The latency variations linked to phase uncertainty. Stable Link Latency: ± 0.7ns uncertainty The results could be improved with better DL calibration But hey are good enough for Bunch By Bunch Measurements

23. Accelerators during Ramp: LHC operations require a clock tolerance of ~2.5 ppm SPS operations require a clock tolerance of ~800ppm We’ll play with Ref_CLK’s around 125Mhz A safe region was found for GBT @ 5Gbps Board 1  125.0 Mhz Board 2  125.0 ± 0.5 Mhz Difference  0.8%  8000 ppm >> 800 ppm We met the specs BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 23 Board 1 (Front-End) Local Ref_CLK 125Mhz Board 2 (Back-End) Variable Ref_CLK 123.5 – 126.5 Mhz 4. GBT implementation on Igloo2 4.8 LHC Clock transmission to the Front-End (Ref_CLK Differences)

24. 4. GBT implementation on Igloo2 4.9 Optical Link Details summary GBT-On-Igloo2 @ 5Gb/s tested and well characterized. GBT protocol in frames of 120 bits: 4 bits header + 84 bits payload + 32 bits FEC Each frame is sent every 25ns synchronized with bunch crossing frequency. Front-End will use the recovered clock in reception for acquisition and transmission. Back-End is continuously sending “dummy” data to maintain synchronization. GBT-on-Igloo2 has shown satisfactory results but many things need to be tested: Recovered CLK quality is good enough for acquisition electronics (Jitter)? Need to test SERDES configuration were the recovered clock is used as TX clock. Verify if recovered clock follows well LHC & SPS Ramp variations (needed frequency sweep) How to include in data Front-End diagnostics information. Need to specify Front-End control protocol through GBT link. The GBT optical link for Igloo2 is almost ready BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 24

25. 5. Electronics Development 5.1 pCVD Diamond Detector Readout ASICs BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 25 QIE10 & ICECAL ASICs compatible with our application. Dynamic range coverage by splitting the pCVD signal Two Front-End possibilities/prototypes to evaluate. Each Front-End will acquire two pCVD channels. Both ASICs are Rad-Hard developments for high energy physics. QIE10: A. Baumbaugh et al. 2013 ICECAL: Kindly provided by E.Picatoste

26. 5. Electronics Development 5.2 Igloo2 UMd Mezzanine (from CMS HCAL) BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 26 Features: Needed to power with 2.5 & 3.3V Power supply 1.2 &1.5V Microsemi Flash Based Igloo2 FPGA Includes VTRx & SFP+ Modules Various possible SERDES Ref_CLK Local oscillator HSMC Samtec Connector 240 pins. JTAG and Debug connectors Signals routed on Diff.Pairs to connector Radiation & active components (Qualifications): Switched Reg.  LHC4913PDU (CERN-DEV ??) FPGA  Igloo2 ( Under characterization ~1KGy? ) PLL  QPLL (CERN-DEV ~100KGy) Oscillator  EPSON EG-2121CA VTRx  (CERN-DEV >10KGy) Status  Layout revision, soon fabrication & assembly Altium Project kindly provided by T.Grassi

27. 5. Electronics Development 5.3 QIE10 Mezzanine Board Features: Power supply 2.5, 3.3 & 5V 2 x QIE10 Channels 3 x Generic trigger inputs Debugging LEDS Level adapters for SLVS & LVDS slow control (Matching with GBTx levels) Matching connector with Igloo2 UMd. Status  Submitted to Fabrication & Assembly BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 27 Radiation & active components (Qualifications): Linear Reg.  TL1963AKTTR ( MOPOS ~1KGy) Readout ASICs  QIE10 (Fermilab >0.5KGy) LVDS drivers & Receivers: DS90LV048 (Atlas ~ 0.7KGy) DS90LV047 (Atlas ~ 0.7KGy) DS90LV027 ( ??) DS90LV001 ( ?? )

28. 5. Electronics Development 5.4 ICECAL_V2 Mezzanine Board BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 28 Features: Power supply 2.5, 3.3 & 5V 1 x ICECAL with 4 Channels 2 x Generic trigger inputs Level adapters for SLVS & LVDS slow control (Matching with GBTx levels) ADC for ICECAL signal digitalization Matching connector with Igloo2 UMd. Status  Need to be re-designed for ICECAL_V3 Radiation & active components (Qualifications): Linear Reg.  TL1963AKTTR (MOPOS ~1KGy) Readout ASICs  ICECAL (UB-Dev under study) ADC @ 40MSPS (AD41240, AD9238… ??) LVDS drivers & Receivers: DS90LV048 (Atlas ~ 0.7KGy) DS90LV047 (Atlas ~ 0.7KGy) DS90LV027 ( ?? ) DS90LV001 ( ?? )

29. 6.Summary To sum-up : Simulations carefully done to characterize current system with long cabling and identify improvements. Studied different acquisition chains and impact of cable on bunch by bunch sigma measurements. Choice of a Front-End/Back-end architecture based on these theoretical studies to get: 1. Suitable dynamic range coverage for a common system without tuning parameters 2. Use of radiation tolerant detector well characterized (pCVD Diamond Detector) 3. Acquisition system @ 40Mhz synchronous with the bunch (SPS & LHC) 4. Low noise measurements for Gaussian tails / halo determination. Currently developing prototype boards for proof-of-concept evaluation (two ASIC candidates to evaluate) Next Steps: First prototype boards are about to come (Igloo2 Umd & QIE10 Mezzanine around End October) GBT-On-Igloo2 adaptation for new board (few modifications to do) Initial tests of the Front-End prototype on the Lab (Slow control, data acquisition, QIE10 interface...) Re-Design of ICECAL_V3 Mezzanine(4 channels in parallel??) New samples soon available by courtesy of UB (E.Picatoste & D.Gascon) Possible PCB reference design that we’ll adapt for our application. To schedule tests on the tunnel near a BWS once the first prototype performance is demonstrated. BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 29

31. Back-Up Slides BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 31

32. BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 32 2. Long Term plans and system design proposal 2.2 QIE10 Compact Front-End in detail

33. 4. GBT implementation on Igloo2 4.10 This has become a collaborative project (Code availability) First release LATOP version available for download (22/07/2014) : In DropBox: https://www.dropbox.com/sh/hs4xzi3sn0cv2ww/AACYpkFhM3hfYAuc9kOqDRWsa In SVN (Use Tortoise or other SVN client): https://svn.cern.ch/reps/be-bi-bl/electronics/bwsdev/studies/BWS_pCVD Diamond detector Readout Electronics/GBT_On_Igloo2/Firmware/GBT_FPGA_Igloo2/LATOP What is provided: Libero 11.3 Project with GBT_on_Igloo2 code: (2014_07_22_GBT_On_Igloo2_M2GL_EVAL_KIT.rar) Features: GBT Protocol (LATOP Version) on Igloo2 with UART communication through USB port. Constraints are not always met, so care must be taken when new changes are performed analysing timing reports. All the necessary VHDL files are in : GBT_On_Igloo2_M2GL_EVAL_KIT\hdl Programming file (stp) available in : GBT_On_Igloo2_M2GL_EVAL_KIT\designer\GBT_On_Igloo2_M2GL_EVAL_KIT\export In case of trouble, just let me know!! jsirvent@cern.ch there are many things to improve.jsirvent@cern.ch Console Application UART_APP_V3.0: (2014_06_09_UART_APP_V3.0.rar) Features: Controls the workflow of the GBT implementation on Igloo2 and checks different signal values and parameters of the link (RX_BITSLIP_NUMBER, Error number…), Boards Auto-Detection. Microsoft Visual Studio 2008 Project: UART_APP_V3.0\UART_APP.sln Executable File: UART_APP_V3.0\Release\UART_APP.exe Readme File: (2014_06_09_Readme.pdf) Features: Short guide to implement the design on the Dev.Kit and run the application BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 33

34. Univ. of Minnesota [1] Fluence runs 1e11 and 2e12 p/cm2 Registers no TMR  Cross-Section = 2e-6 cm2 Registers TMR  Cross-Section < 5e-7 cm2 Combinatorial logic  Cross-Section < 1.5e-4 cm2 PLL SEU 400 observed over 10e11 p/cm2  Cross Section = 4e-9 cm2 No SEU seen on TMR shift register No SET seen TID Fail @ ~100kRad (2e12p) “The failure likely because too much current was drawn, although further testing is needed to determine how much current the chip can handle” Future Electronics [2] Non Destructive SEL Total Fluence 1.07e9 ant LET levels up to 30.86MeV-cm2/mg. SEL LET th @ 100 deg > 22.5MeV-cm2/mg (Proton/Neutron Inmune SEL) Non destructive SEL found at LET = 24MeV-cm2/mg Configuration memory SEU: No configuration upsets detected at fluence 2.83e9 Heavy ions. Data SEU: Flip Flops (Total Fluence = 4.35e11 n/cm2) : 1.13e5 FIT @ 40000 feet / 218e3 FIT @ ground level per million FF Large Ram Blocks (Total Fluence = 1.7e11 n/cm2): 1.75e5 FIT @ 40000 feet / 340.6 FIT @ ground per million bits. Micro SRAM Blocks (Total Fluence = 1.7e11 n/cm2): 9.04e4 FIT @ 40000 / 175.3 FIT @ ground per million bits. Single Event Functional Interrupts (SEFI): MSS (Total Fluence = 7.11e9 n/cm2)  0 SEFIs Found PLL (Total Fluence = 3.29e10 n/cm2)  0 SEFIs Found Microsemi Corporation [3] TID resistance ~ 80-90 kRad  “Icca increase due to isolation Flash Switch, gradually turning on by ionizing radiation.” [1] A. Finkel, J. Mans, J. Turkewitz, Radiation Testing of an Igloo2 Fpga. University of Minesota. January 14 th, 2014 [2] Future Electronics. Microsemi Corporation Igloo2 and SmartFusion2 65nm Commercial Flash FPGAs Interim Summary of Radiation Test Results. June 20, 2014. [3] JJ Wang et al. Using Microsemi Flash-Based FPGA in radiation Environment. Workshop on FPGAs for High Energy Physics BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 34 Back-up Slides Igloo2 Irradiation reports:

35. GBT-FPGA One unified core for multiple usersGBT-FPGA One unified core for multiple users. Manoel Barros Marin, PH/ESE/BE Students-Fellows seminar (05/02/2014). Back-up Slides GBT-FPGA Project (Latency Optimized Release with clock alignment) BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 35

36. 4. GBT implementation on Igloo2 4.1 GBT-FPGA Project (Some information and resources) Part of the Radiation Hard Optical Link Project: Development of firmware for Back-ends to communicate with GBTx – based front-ends and GBTx Emulation. Coverage of 8b/10b, Wide-Bus and GBT mode (Reed-Solomon Based) Public SharePoint: https://espace.cern.ch/GBT-Project/GBT-FPGA/default.aspxhttps://espace.cern.ch/GBT-Project/GBT-FPGA/default.aspx Public SVN Releases : https://svn.cern.ch/reps/ph-ese/be/gbt_fpga/tagshttps://svn.cern.ch/reps/ph-ese/be/gbt_fpga/tags Mailing List: gbt-fpga-users@cern.ch, GBT-FPGA-support@cern.chgbt-fpga-users@cern.chGBT-FPGA-support@cern.ch Contacts for support: sophie.baron@cern.ch, manoel.barros.marin@cern.chsophie.baron@cern.chmanoel.barros.marin@cern.ch Last news: Standard (STD)  Data Readout(DAQ) Low and Deterministic latency (LATOP) )  FE control & Time, Trigger and control (TTC) Support & code available for (Dev. Kits): Xilinx Virtex 6 / 7 & Kinex 7 Altera Cyclone V & Statrix V BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 36

37. 1. Cable measurements campaign. 2 nd Experiment (lab testing): Equipment works well, only delay of 8ns 4 ns 8 ns CK 50 Cable Connection -PicoSecond 2600C: Pulse generator  1 - 100ns Selectionable delay Repetition Rate  1-100KHz Vo  45V (-70dB) Zo  50 ohm -LeCroy Scope: Sampling Freq  5Gsps Scale  2ns/div Zin  50 ohm -Testing pulses characteristics: Rise time  419ps Fall time  837ps Pulse width  700ps System delay  8ns

38. 1. Cable measurements campaign. 2 nd Experiment (Pulse distortion with Square pulse): Square pulse ~4ns: Rise: 407ps  596ps Falling: 876ps  3.436ns Width: 2.464ns  3.298ns Whole Pulse: 3.747ns  7.330ns (Δ195%) Attenuation: 3V  1.75V (-4.68dB) *Yellow: Input *Pink: Output

39. 1. Cable measurements campaign. 2 nd Experiment (Pulse distortion with ~1.5ns pulse): Square pulse ~1.5ns: Rise: 378ps  606ps Falling: 860ps  4.375ns Width: 763ns  1.369ns Whole Pulse: 2.001ns  6.350ns (Δ317%) Attenuation: 2.75V  1V (-8.7dB) *Yellow: Input *Pink: Output Beware the long tails!! 25ns

40. Front-End: A) BLM Style (Quick assembly): Ewald’s scheme -40dB 40dB -6dB AC DC pCVD Cividec Amplifier Cividec Attenuator Cividec AC-DC Splitter Cividec Diamond Detector Mini-Circuits DC-4GHz Splitter -6dB Mini-Circuits DC-4GHz Splitter -6dB 34dB -12dB -52dB -6dB HV 12V DC Tunnel Surface

41. People and experiments interested on GBT on Igloo2: Tullio Grassi (+), Tom O’baron(+)(++), Frédéric Machefert(*)(++), Chistophe Beigbeder (*)(++), Us (**). Many others are wellcome!! Just contact me (jsirvent@cern.ch) !jsirvent@cern.ch (+)CMS experiment: Compact Muon Solenoid Experiment (++)LHCb collaboration: Large Hadron Collider beauty collaboration (*)LAL : Laboratoire de l´Accélérateur Linéaire (**)Beam Instrumentation Group Why such interest? : Igloo2 Flash based technology (“SEU Inmune Fabric”) with 5G SERDES. Good results obtained with previous family (ProAsic3). Applications where high speed data transfer is needed in areas with radiation. Promising irradiation results (more test will come more soon). BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 41 4. GBT implementation on Igloo2 4.10 This has become a collaborative project

42. 4. GBT implementation on Igloo2 4.4 Latency Optimized Clock management on Igloo2 BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 42

43. 43 0.3 Clock relationships: Understanding some details of the clock recovery

44. 44 3. Ref. Frequency tolerance 3.0 How to transmit LHC Clock to the Front-End Electronics TX_PLL x3 LHC Clock 40.079Mhz TX_SERDES SERDES Ref_Clock 120.237Mhz Surface FPGA Tunnel FPGA RX_SERDES RX_PLL /6 Optial Link GBT @ 4.809Gbps SERDES EPCS_RX_CLK 240.474Mhz (Word_Clock) Local SERDES REF_CLK 120Mhz LHC Clock 40.079Mhz (RX_Frame_Clock)

45. 4. Clocks Frequency Stability 4.1 Freq Histogram of the TX & RX Word CLKs (250Mhz) 45 EPCS_TX_CLK (Board 1) EPCS_RX_CLK (Board 2) EPCS_TX_CLK (Board 2) EPCS_RX_CLK (Board 1) Clocks Stability: For Both clocks (TX_WORD_CLK & RX_WORD_CLK), independently of their Ref_CLK source it was observed certain frequency dispersion. EPCS_TX_CLK  STDEV ~ 6.1MHz (24400ppm) Frame_TX_CLK  STDEV ~ 41kHz (985ppm) EPCS_RX_CLK  STDEV ~ 3.7MHz (14800ppm) Frame_RX_CLK  STDEV ~ 45kHz (1081ppm) Possible Reasons: Not really well understood Part of the SERDES Specifications? More care needed on routing/ Implementation? Some questions to think about: Impact on system performance? Could we tolerate this variations?

46. 46 4. Clocks Frequency Stability 4.2 Freq Histogram of the TX & RX Frame CLKs ( After PLLs 41.6Mhz) Frame_TX_CLK (Board 1) Frame_RX_CLK (Board 2) Frame_TX_CLK(Board 2) Frame_RX_CLK (Board 1) Clocks Stability: For Both clocks (TX_WORD_CLK & RX_WORD_CLK), independently of their Ref_CLK source it was observed certain frequency dispersion. EPCS_TX_CLK  STDEV ~ 6.1MHz (24400ppm) Frame_TX_CLK  STDEV ~ 41kHz (985ppm) EPCS_RX_CLK  STDEV ~ 3.7MHz (14800ppm) Frame_RX_CLK  STDEV ~ 45kHz (1081ppm) Possible Reasons: Not really well understood Part of the SERDES Specifications? More care needed on routing/ Implementation? Some questions to think about: Impact on system performance? Could we tolerate this variations?

47. Back-up Slides QIE10 Architecture BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 47 QIE10 Characteristics and functionality(*): Rad-Hard Charge-Integrating ASIC (25ns) Fast, Wide dynamic range, Dead-Timeless ADC (Latency: only 4x25ns) Very High dynamic range: 3.2fC  340pC (Fits well our initial estimations!!) LSB 3.2fC (Almost MIP for pCVD) Non linear charge digitalization scheme: 6 bit FACD mantissa + 2 Exp (4 Ranges) TDC capability: Produces TDC info based on the Rising/falling edge of pulse (2 configurable 8bits thresshold levels) Inputs: Reset (CLK Alignment) Charge signal (from pCVD) CLK Programmable stuff ( Thressholds, Pedestrials…) Outputs: Q : Charge Integral T1: Arrival time (500ps resolution) T2: Falling time (500ps resolution) QIE10p4 Already available! QIE10p5 soon (maybe also available) * “CMS Specifications Document for the QIE10 ASIC. 2010” http://indico.cern.ch/getFile.py/access?contribId=10&resId=0&materialId=0&confId=124743 47

48. BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 48 Back-up Slides QIE10 Response Mapping

49. Back-up Slides ICECAL Architecture BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 49

50. BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 50 2. Studying Possibilities 2.4 Current system simulation (Impact on Profiles 50ns) Gaussian Goodness-of-fit evaluation through SSE (Sum of Squares Due to Error) VS Cable Length (m) Bunch Sigma Error VS Cable Length(m) Sigma errors increase with length and sigma difference Gaussian fit quality decreases with distance and Sigma difference

51. BE-BI-BL Jose Luis Sirvent Blasco (jsirvent@cern.ch) 51 2. Studying Possibilities 2.4 Current system simulation (Impact on Profiles 75ns) Gaussian Goodness-of-fit evaluation through SSE (Sum of Squares Due to Error) VS Cable Length (m) Bunch Sigma Error VS Cable Length(m) Sigma errors increase with length and sigma difference Gaussian fit quality decreases with distance and Sigma difference

52. 4. Impact of # points per sigma in Sigma Error