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Arithmetic Circuits I
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2 Iterative Combinational Circuits Like a hierachy, except functional blocks per bit
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3 Adders Great example of Iterative design Design a 1-bit adder circuit, then expand to n-bit adder Look at ♦ Half adder – which is a 2-bit adder ♦ Inputs are bits to be added Outputs: result and possible carry ♦ Full adder – includes carry in, really a 3-bit adder
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4 Half Adder S = X Y C = XY Fig. 4-2
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5 Full Adder Three inputs. Two are operand bits, third is C in Two outputs: sum and carry
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6 K Map for S What is this? In a half adder the sum bit: S = X Y
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7 K Map for C In a half adder the carry bit: C = XY
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8 Using two half Adders to Build a Full Adder Full adder functions Half adder functions S = X Y C = XY
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9 Two Half Adders (and an OR) Fig. 4-4
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10 Ripple-Carry Adder Straightforward – connect full adders C 4 : Chain carry-out to carry-in of FA of bits A 4 & B 4 ♦ C 0 in case this is part of larger chain ♦ otherwise just set to zero
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11 Hierarchical 4-Bit Adder We can easily use hierarchy here Design half adder Use in full adder Use full adder in 4-bit adder
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12 Binary Subtraction Example: ♦ Let M = (19) 10 ; N = (30) 10 ; How is M-N computed? In decimal notation: (19) 10 – (30) 10 = - (11) 10 In binary: (10011) 2 - (11110) 2 = - (01011) 2
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13 Using 2’s & 1’s Complement Representation of Signed Numbers People use complemented interpretation for signed numbers ♦ 1’s complement ♦ 2’s complement
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14 1’s Complement Given: binary number N with n digits 1’s complement is defined as (2 n – 1) - N Note that (2 n – 1) is a number with n bits, all of them 1 ♦ For n = 4, (2 n – 1) = (15) 10 = 1111
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15 Example: Find 1’s Complement of N =101 1001 Notice that 1’s complement is complement of each bit n= 7 ; 2 n - 1 1111111 - N1011001 1’s Compl.0100110 1’s Complement of N is (2 n – 1) - N
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16 2’s Complement Given: binary number N with n digits 2’s complement defined as 2 n – N for N 0 0 for N = 0 Note that since 1’s complement is (2 n – 1) – N ♦ 2’s complement is just a 1 added to 1’s complement
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17 Example: Find 2’s Complement of N =101 1001 To find 2’s complement of N ♦ Find is 1’s complement of N then add 1 N1011001 1’s Compl.0100110 +10000001 2’s Compl.0100111 2’s Complement of N is 2 n - N
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18 Important Property Complement of a complement generates original number
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19 Subtraction Using 2s Complement: Compute M-N 1.Add 2’s complement of N to M ♦ M + (2 n – N) = { M – N + 2 n } = F 2.If M N, this addition will generate a carry, 2 n Discard carry; the result gives the answer of M-N which is positive 3.If M < N, no carry; M-N is negative; the answer is –(N-M). To compute the answer: Take 2’s complement of F 2 n – F = 2 n - { M – N + 2 n } = N-M Place minus sign in front { - (N-M) }; This is the answer 4.Hence to compute (M-N): do 1 & 2 if M N; OR 1 & 3 If M < N
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20 Compute M-N; Example 1: M > N M = (84) 10 = (101 0100) 2 N = (67) 10 = (100 0011) 2; ♦ 2’s comp N = ( 011 1100 ) + 1 = 011 1101 M1010100 + 2’s comp N0111101 Sum10010001 M > N; Carry generated; Discard carry; Result is positive M - N 17 10
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21 Compute M-N; Example 2: M < N; M = 67 10 = 100 0011; N = 84 10 = 101 0100 M = 100 0011 minus N = 101 0100 No end carry ♦ Answer: - (2’s complement of Sum) Answer: - 0010001 M1000011 + 2’s comp N0101100 Sum 1101111 We said numbers are unsigned. What does this mean? How is -17 10 represented?
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22 Subtractor Compute M-N ♦ Add 2’s complement of N to M: M + (2 n – N) If M >= N, need only “one adder” and a “complementer of N” to do the subtraction. If M < N, we also need to take 2’s complement of adder’s output to produce magnitude of result 2 n -{ M + (2 n – N)} = N-M
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23 Adder-Subtractor Design: (A+B) OR (A-B) Output is result if A >= B; Discard carry Output is 2’s complement of result if B > A S is low for add, high for subtract Inverts each bit of B if S is 1 Fig. 4-7 Add 1 to make 2’s complement
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24 Signed Binary 1.Signed magnitude ♦ Left bit is sign, 0 positive, 1 negative ♦ Other bits are number 2.2’s complement 3.1’s complement
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25 Example in 8-bit byte Represent -9 10 = -(0000 1001) in different ways “Signed magnitude” of - (0000 1001) is 1000 1001 “Signed 1’s Complement” of - (0000 1001) is 1111 0110 “Signed 2’s Complement” of - (0000 1001) is 1111 0111
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26 Observations (assume 4-bit numbers) 1’s C and Signed Magnitude have two zeros 2’s C has more negative numbers than positive All negative numbers have 1 in highest-order bit
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27 Advantages/Disadvantages Signed magnitude & One’s complement has a positive and negative zero Two’s complement is most popular ♦ Arithmetic operations easy
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28 Two’s Complement Addition easy on any combination of positive and negative numbers To compute A - B ♦ Take 2’s complement of subtrahend B to produce -B ♦ Add to A This performs A + ( -B), same as A – B
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29 Examples Assume we use 2’s complement representation of signed numbers Store each number in 8 bits 6 = (0000 0110) ; 13 = (0000 1101) -6 = (1111 1010) ; -13 = (1111 0011) Addition ♦ 6 + 13 ♦ -6 + 13 ♦ 6 + (- 13) ♦ (-6) + (-13) Subtraction ♦ -6 - (-13) ♦ 6 - (- 13)
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30 Overflow Overflow means that result can not be represented with the number of bits used Two cases of overflow for addition of signed numbers ♦ Two large positive numbers overflow into sign bit Not enough bits for result ♦ Two large negative numbers added Same – Not enough bits for result
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31 Examples: Work on Board Assume 1- We use “2’s complement representation” of signed numbers 2- Store each number in 4 bits : b 3 b 2 b 1 b 0
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32 Example 1 7 + 7 Overflow: can not represent 14 using only 4 bits Generates NO CARRY, C 4 = 0
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33 Example 2 -7 - 7 Overflow: can not represent -14 using only 4 bits Generates CARRY, C 4 = 1
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34 Example 3 4 + 4 Overflow: can not represent 8 using only 4 bits Generates NO CARRY, C 4 = 0
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35 Example 4 7 – 7 NO Overflow Generates CARRY, C 4 = 1
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36 Overflow Detection Condition for overflow: ♦ either C n-1 or C n is high, but not both ♦ 7 + 7; only C n-1 (C 3 ) is high ; overflow ♦ -7 - 7; only C n (C 4 ) is high ; overflow ♦ 4 + 4; only C n-1 (C 3 ) is high ; overflow ♦ 7 – 7; BOTH C n-1 & C n (C 4 & C 3 ) are high; no overflow --------------------------------------------------------- Fig. 5-9 Overflow Detection for Addition and Subtraction Fig. 4-8
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