1. Memory Management memory hierarchy programs exhibit locality of reference - non-uniform reference patterns temporal locality - a program that references a memory location once is likely to re-reference it in the future, e.g., multiple accesses to the same variable, revisit instructions in a loop spatial locality - a program that references a memory location once is likely to reference a near-by memory location in the future, e.g., sequentially traversing an array, sequentially fetching instructions

2. Memory Management since you cannot afford a huge amount of the fastest storage, instead use several levels of increasingly larger, cheaper storage and exploit locality by keeping copies of recently used memory contents in the higher levels registers on-chip 32-128 registers 250 picoseconds L1 cache on-chip 16 KB - 64 KB 1 nanosecond L2 cache SRAM 1 MB - 8 MB 5 nanoseconds main memory DRAM 64 MB - 512 MB 100 nanoseconds

3. Memory Management since you cannot afford a huge amount of the fastest storage, instead use several levels of increasingly larger, cheaper storage and exploit locality by keeping copies of recently used memory contents in the higher levels registers on-chip 32-128 registers 250 picoseconds L1 cache on-chip 16 KB - 64 KB 1 nanosecond L2 cache SRAM 1 MB - 8 MB 5 nanoseconds main memory DRAM 64 MB - 512 MB 100 nanoseconds >> -- flash memory filling gap virtual memory disk tens of GB per disk 5 milliseconds

4. Memory Management key idea - only keep active pieces of program in memory and in caches OS control over main memory / virtual memory transfers hardware control over cache / main memory transfers compiler control over register / main memory transfers called a "hit" if the object to access is found in the current level, or "miss" if you have to obtain from lower level if hit rates in top levels of hierarchy are high enough, then the average memory access time corresponds to the speed of the caches

5. Memory Management memory hierarchy policies fetch policy - when to bring into higher level – demand fetch - bring in when necessary – prefetch placement policy - where to put into higher level replacement policy - when full, what to replace/evict out of higher level write policy - when to update lower leve – write-through - update lower level with all changes to the higher level – write-back - update lower level only when evicted from higher level

6. Virtual Memory paging - divide up program and data into fixed-length pieces (e.g., 4K bytes) – invisible to software other than OS segmentation - divide up program and data into variable- length logical sections – logical segment names will be produced by compiler and will be visible to assembly lang. programmer, compiler, linker, and loader OS manages page and segment misses since so slow to retrieve from disk hardware turns miss into "fault", that is, an interrupt that invokes the OS and causes process switch (i.e., run another process while missing page or segment is read in from disk)

7. Virtual Memory address translation for paging and/or segmentation through tables - controls allocation in memory, name mapping, and protection, usually multiple levels of tables are defined each process has its own page and/or segment tables - each can run in its own "virtual address space" and not be aware that physical memory is shared PTE - page table entry - contains: presence bit, main memory page frame number, protection bits STE - segment table entry - contains: presence bit, disk address, main memory address, length, protection bits

8. Virtual Memory for write-back policy, a modified (a.k.a. dirty, changed) bit is used in the table entry to indicate if block must be rewritten to disk on replacement often a referenced (a.k.a. accessed) bit is included in the table entry to indicate if the block has been recently referenced TLB - translation lookaside buffer - small address cache containing recently-used PTEs/STEs, since it would be very slow to have to access the (multiple level) page or segment tables in memory each time before accessing an instruction or data word

9. Virtual Memory cache like paging (fixed-length) but smaller blocks (e.g., 32 bytes) miss is handled by hardware since on cache miss the missing block can be obtained from main memory very quickly separate L1 caches for instruction and data so that pipeline can access them at the same time L2 usually unified - holds both instructions and data

10. Virtual Memory context switch save enough information (or "state") about the currently running process to be able to later resume it - involves CPU registers and memory mapping