1. Advanced Digital Design Asynchronous Design: DI Methods A. Steininger Vienna University of Technology

2. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 2 Outline Delay Insensitive design - principle Delay Insensitive design - principle NULL-Convention Logic NULL-Convention Logic Code conditions for DI logic Code conditions for DI logic Four-State Logic Four-State Logic

3. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 3 „The control flow requires agreement between source and sink. For this purpose they need to communicate“ „The control flow requires agreement between source and sink. For this purpose they need to communicate“ Source indicates capture condition for sink. Source indicates capture condition for sink. Sink indicates issue condition for source. Sink indicates issue condition for source. Asynchronous Philosophy „HANDSHAKE“ recall

4. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 4 Handshake Principle SRCSNK f(x) When it is valid and consistent When SNK has consumed the previous one When can SNK use its input? When can SRC apply the next input? REQ: „Data word valid, you can use it“ ACK: „Data word consumed, send the next“ * recall

5. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 5 A very Important Detail The handshake establishes a closed-loop control for the data flow between sender and receiver The handshake establishes a closed-loop control for the data flow between sender and receiver This makes operation more robust than in the synchronous (= open-loop) case This makes operation more robust than in the synchronous (= open-loop) case The art of asynchronous design is to make these closed loops interoperate properly The art of asynchronous design is to make these closed loops interoperate properly This is much more complicated than a synchronous design. This is much more complicated than a synchronous design. Time is continuous now, no more discrete Time is continuous now, no more discrete recall

6. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 6 Bundled Data at a Glance single-rail data coding single-rail data coding 4- or 2-phase handshake 4- or 2-phase handshake Source: [Sparso 06] recall

7. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 7 Very disappointing… For a closed loop we need to measure the quantity of interest For a closed loop we need to measure the quantity of interest So far we have not done that: So far we have not done that: We have not measured validity & consistency We have not measured validity & consistency We have used time as an indirect measure instead We have used time as an indirect measure instead Thus Bounded Delay methods do not provide the benefits of a closed loop Thus Bounded Delay methods do not provide the benefits of a closed loop BUT: Can we measure validity & consistency at all? BUT: Can we measure validity & consistency at all?

8. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 8 Criticality of ACK cannot measure „act of capturing“ as an event cannot measure „act of capturing“ as an event use latching command instead use latching command instead fork produces race between trigger process and next data wave fork produces race between trigger process and next data wave race is uncritical (but still exists!) race is uncritical (but still exists!) SRCSNK f(x) L2 „capture!“ recall *

9. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 9 Criticality of REQ SRCSNK f(x) cannot use issue trigger as an event: cannot use issue trigger as an event: produces unacceptable race between data and REQ produces unacceptable race between data and REQ must introduce timer (bounded delay) must introduce timer (bounded delay) OR: find better event (downstream) OR: find better event (downstream) completion detection recall *

10. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 10 Closed Loop Timing ACK signal no synchrony assumed! no synchrony assumed! (relatively) safe (relatively) safe  “act of latching” done ? ACK “timing closure”

11. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 11 Closed Loop Timing REQ signal no synchrony assumed! no synchrony assumed!  BD: delay element defines worst case, loop not closed ! REQ ()

12. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 12 Closed Loop Timing REQ signal no synchrony assumed! no synchrony assumed! DI: completion detection measures validity, loop is closed ! DI: completion detection measures validity, loop is closed ! REQ (CD)

13. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 13 Completion Detection In order to judge when data are valid & consistent we need to be able to see when this is NOT the case In order to judge when data are valid & consistent we need to be able to see when this is NOT the case not possible with Boolean logic not possible with Boolean logic need representation for INVALID need representation for INVALID a REQ in parallel to data (bundled data) will always cause a race a REQ in parallel to data (bundled data) will always cause a race need more than two signal states for every individual bit (!) need more than two signal states for every individual bit (!) need more than one rail per bit need more than one rail per bit

14. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 14 Multi-level Logic use more than two (e.g. three) voltage levels per rail use more than two (e.g. three) voltage levels per rail allows to express „invalid“ in the currently „forbidden“ area between HI and „LO“ allows to express „invalid“ in the currently „forbidden“ area between HI and „LO“ requires two thresholds for every gate input requires two thresholds for every gate input output must be able to drive three different levels reliably output must be able to drive three different levels reliably causes substantial technological problems causes substantial technological problems not further pursued

15. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 15 Our Options We must only use consistent input vectors We must only use consistent input vectors How can we tell an input vector is consistent? How can we tell an input vector is consistent? (1) use TIME to mark consistent phases synchronous approach / global time base synchronous approach / global time base asynchronous/bounded delay asynchronous/bounded delay (2) use CODING to add information asynchronous/delay insensitive asynchronous/delay insensitive recall *

16. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 16 Terminology consistent DW: all bits belong to the same context valid signal: result of function applied to consistent DW recall

17. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 17 Add the value NULL to the alphabet Signal X X.aX.bmeaning 00 NULL (N) 01 TRUE (T) 10 FALSE (F) 11illegal X X.a X.b two-rail coding: NULL Convention Logic „DATA“

18. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 18 TFN TTFN FFFN NNNN ANDTFNTTTN FTFN NNNN OR TF FT NN NOT NCL Functions naive approach: if any input is „N“ then output „N“

19. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 19 NCL Flow Control NULL waves enframe DATA waves NULL waves enframe DATA waves Completion detection = check wether all bits are „DATA“ (completeness of DATA) Completion detection = check wether all bits are „DATA“ (completeness of DATA) NULL TRUE FALSE TRUE NULL TRUE FALSE TRUE FALSENULL t consistent DATA *

20. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 20 Still Problems … What about this situation? Fast bits may catch up with a slow bit from the previous word. The word containing the „old“ bit is considered consistent! NULL TRUE FALSE TRUE NULL TRUE FALSENULL t consistent DATA DATA NULL output *

21. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 21 Solution Principle Enforce „completeness of NULL“ as well: Enforce „completeness of NULL“ as well: The output must not go to NULL before all inputs have changed to NULL The output must not go to NULL before all inputs have changed to NULL In a closed loop configuration this keeps the slow paths in synchrony with the fast ones In a closed loop configuration this keeps the slow paths in synchrony with the fast ones (=> timing closure, not validity!) We need different truth table when output is NULL

22. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 22 TFN TTFN FFFN NNNN ANDTFNTTFD FFFD NDDN Two Truth Tables for DATA waves for NULL waves D … DATA (T or F) must hold output in last valid state before new input is complete must hold output in last valid state before new input is complete need „hysteresis“ need „hysteresis“ need to consider current output in truth table need to consider current output in truth table

23. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 23 A B Y‘ NFT NTFNTFNTF NTFNTFNTFNTFNTFNTFNTFNTFNTF NNNNTFNFFNFFFFFFFFNTTTTTTTT Y Y A B Y‘ T F F N N N FN & Feedback Gate unstable (Y  Y‘) *

24. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 24 No more Problems … Have we solved the problem? YES! The output now remains at DATA with the slowest bit, thus inhibiting (via the closed loop) the fast bits to convey the next DATA wave. NULL TRUE FALSE TRUE NULL t consistent DATA DATANULL output *

25. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 25 The desired hysteresis requires an NCL gate to hold its output until all inputs are DATA or all inputs are DATA or all inputs are NULL all inputs are NULL need storage capability (or feedback loop) even in combi- national gate Mem X1.a X1.b X1 X2.a X2.b X2 Y.a Y.b Y Mem NCL Gates

26. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 26 [G. Sobelmann, K. Fant: CMOS Circuit Design of Threshold Gates with Hysteresis] p- and n-stack not dual memory cell at output NCL Gate Implementation Mem X1.a X1.b X1 X2.a X2.b X2 Y.a Y.b Y Mem figure shown for one output rail only CMOS-Transistors only but no standard cells *

27. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 27 The Charme of NCL self-regulating data flow self-regulating data flow in a NULL initialized circuit a DATA front will propagate towards the output in a NULL initialized circuit a DATA front will propagate towards the output alternating waves of NULL and DATA pace the data flow (like the „clock“) alternating waves of NULL and DATA pace the data flow (like the „clock“) based on direct assessment of validity & consistency based on direct assessment of validity & consistency no delay assumptions necessary (ideally), no „worst case“, … no delay assumptions necessary (ideally), no „worst case“, … globally applicable solution globally applicable solution

28. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 28 Validity and Consistency Consistency (multiple bits @ input) Consistency (multiple bits @ input) all bits that are combined are valid and belong to the same context all bits that are combined are valid and belong to the same context Validity (single bit @ output) Validity (single bit @ output) the bit is the stable result of a combination of consistent bits the bit is the stable result of a combination of consistent bits Consistency implies validity (per definition) but NOT vice versa! *

29. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 29 Val. & Consistcy. in NCL Validity: Validity: output is changed only when consistent input is available („hold“ in truth table) output is changed only when consistent input is available („hold“ in truth table) coding ensures direct transistion from valid code to another (NULL is valid but spacer only) coding ensures direct transistion from valid code to another (NULL is valid but spacer only) continuous validity continuous validity Consistency: Consistency: NULL spacer between DATA waves allows identification of context NULL spacer between DATA waves allows identification of context synchronization of context by virtue of „completeness of NULL“ condition synchronization of context by virtue of „completeness of NULL“ condition no timing assumptions! CODING indicates consistency *

30. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 30 What about sync. & BD? Timing ensures that every data item is both valid and consistent at the time it is used: Timing ensures that every data item is both valid and consistent at the time it is used: choice of clock period (sync) choice of clock period (sync) choice of delay values (BD) choice of delay values (BD) In contrast to NCL (temporary) invalidity & inconsistency of data is admitted. In contrast to NCL (temporary) invalidity & inconsistency of data is admitted. No explicit measures (other than timing) are taken/necessary to cope with these issues. No explicit measures (other than timing) are taken/necessary to cope with these issues.

31. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 31 synchronous model synchronous model known bounds for delays, global timing known bounds for delays, global timing bounded delay model (BD, fundamental) bounded delay model (BD, fundamental) known bounds for absolute delays, local timing known bounds for absolute delays, local timing scalable-delay-insensitive model (SDI) scalable-delay-insensitive model (SDI) bounds for relative deviation between delays known bounds for relative deviation between delays known quasi-delay-insensitive (QDI) quasi-delay-insensitive (QDI) output paths of a fork have same delay output paths of a fork have same delay delay insensitive (DI) delay insensitive (DI) no restrictions on delays (just finite) no restrictions on delays (just finite) Delay Models recall

32. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 32 validity & consistency directly visible validity & consistency directly visible no timing assumptions required (ideally) no timing assumptions required (ideally) „delay insensitive“ (ideally) „delay insensitive“ (ideally) suitable for CMOS implementation suitable for CMOS implementation  coding of one bit on two rails  2 memory cells per combinational output  efficiency: 50% of the data flow are unproductive NULL waves patented und industrially used patented und industrially used NCL: A Brief Summary

33. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 33 NCL at a Glance dual-rail data coding dual-rail data coding 4-phase handshake 4-phase handshake Source: [Sparso 06]

34. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 34 Our Options We must only use consistent input vectors We must only use consistent input vectors How can we tell an input vector is consistent? How can we tell an input vector is consistent? (1) use TIME to mark consistent phases synchronous approach / global time base synchronous approach / global time base asynchronous/bounded delay asynchronous/bounded delay (2) use CODING to add information asynchronous/delay insensitive asynchronous/delay insensitive recall * ARE THERE OTHER CODING OPTIONS?

35. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 35 completion detection needs ONE UNIQUE event: (C1) Identification of every context switch It must be possible to clearly separate two successive data words under all circumstances (C2) Unique context membership The transition from one valid code word to the next must be unambiguous, i.e. no intermediate state may be a valid code Conditions for DI Coding * =>prohibit having no event =>prohibit having more than one event

36. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 36 (C1) Identification of every context switch It must be possible to clearly separate two successive data words under all circumstances Conditions for DI coding 0,0,0 ? *

37. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 37 (C1) Identification of every context switch It must be possible to clearly separate two successive data words under all circumstances (C2) Unique context membership The transition from one valid code word to the next must be unambiguous, i.e. no intermediate state may be a valid code Conditions for DI coding *

38. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 38 (C2) Unique context membership The transition from one valid code word to the next must be unambiguous, i.e. no intermediate state may be a valid code Conditions for DI coding 0,0,01,0,01,0,11,1,1 ? *

39. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 39 (C1) Return to NULL forces separation between successive data waves (C1) Return to NULL forces separation between successive data waves (C2) Coding scheme guarantees direct switch from one legal value to next (only one rail changes!) (C2) Coding scheme guarantees direct switch from one legal value to next (only one rail changes!) X Signal X X.a X.b X.bvalue 0 0NULL 0 1TRUE 1 0FALSE 1 1illegal What about NCL‘s Coding

40. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 40 ABY 000 010 100 111 0,1 1,0NULL & A B Y 00 NN N Synchronization of Waves no glitch! successive „0“s clearly separable *

41. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 41 More Efficient Coding? NCL employs a 4-phase (RTZ) version of transition signaling. NCL employs a 4-phase (RTZ) version of transition signaling. The „return to zero“ is due to the NULL waves. The „return to zero“ is due to the NULL waves. The NULL waves are unproductive and hence undesired. The NULL waves are unproductive and hence undesired. Can we employ a 2-phase (NRZ) signaling instead? Can we employ a 2-phase (NRZ) signaling instead?

42. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 42 Transition Signaling Transition Signaling NULL-Convention Logic NULL-Convention Logic NCL vs. Trans. Signaling A0A0 A1A1 A=0A=1 A=0 A0A0 A1A1 A=1 A=0

43. Transition Signaling Protocol high throughput high throughput difficult to implement: how to attain transition-based completion detection? difficult to implement: how to attain transition-based completion detection? Alternative: 2-phase protocol based on state signaling Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 43 Source: [Sparso 06]

44. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 44 Four-State Logic (FSL) Use 2 codes per logic value Use 2 codes per logic value X X.a X.b two-rail coding:

45. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 45 Alternate code sets („phase“) Alternate code sets („phase“) Completion detection: Check whether all bits belong to the same phase Completion detection: Check whether all bits belong to the same phase H L H h l l h L L H H l l h hH t konsistent phase 0 consistent phase 1 NULL TRUE FALSE TRUE NULL TRUE FALSE TRUE FALSENULL NCL FSL FSL Flow Control *

46. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 46 FSL AND-Gate: Truth Table YlhLH lll** hlh** L**LL H**LH IN_1 IN_2 * … hold last valid output

47. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 47 Four-State Logic (FSL)  An FSL gate holds its output until all inputs are in the same phase need storage capability (or feedback loop) even in combi- national gate Mem X1.a X1.b X1 X2.a X2.b X2 Y.a Y.b Y Mem

48. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 48 (C1) Phase change forces separation between successive data waves (C1) Phase change forces separation between successive data waves (C2) Coding scheme guarantees direct switch from one legal value in one phase to legal value in next phase (only one rail changes!) (C2) Coding scheme guarantees direct switch from one legal value in one phase to legal value in next phase (only one rail changes!) still this is different from transition signaling! FSL and Code Conditions

49. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 49 ABY 000 010 100 111 0,1 1,0 & A B Y 00 00 11 Synchronization of Waves no glitch! successive „0“s clearly separable *

50. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 50 FSL retains all the charme of NCL FSL retains all the charme of NCL FSL provides double data throughput FSL provides double data throughput  implementation of 2-phase scheme requires more efforts => 4-phase is preferred for computation intensive tasks, and 2-phase for communication FSL: A Brief Summary

51. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 51 FSL at a Glance dual-rail (level based) data coding dual-rail (level based) data coding 2-phase handshake 2-phase handshake X1.a X1.b Xn.a Xn.b … Ackab 0000LO00 HI11 1111LO01 HI10 valid X1 Xn Ack …

52. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 52 need to determine clock period need to determine clock period circuit functionality is technology dependent circuit functionality is technology dependent considerable design efforts, large design loops considerable design efforts, large design loops need to make worst-case assumptions need to make worst-case assumptions necessarily pessimistic necessarily pessimistic no robustness wrt. exceeding them no robustness wrt. exceeding them need to maintain global synchrony need to maintain global synchrony clock distribution problems clock distribution problems power consumption problems power consumption problems Gain of Delay Insensitive *

53. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 53 Comparing the Styles single railmultirail delay modelboundedQDI ACKexplicit handshake REQexplicitcompl. det. handshake style 4-phase (RTZ) 2-phase (NRZ) data coding single railbundled data multirailNCLFSL, LEDR

54. Test yourself… How is the issue condition enforced in DI logic? How is the issue condition enforced in DI logic? We still have an ACK line We still have an ACK line How is the capture condition enforced in DI logic? How is the capture condition enforced in DI logic? completion detection on code completion detection on code Why do we need the NULL wave in NCL then? Why do we need the NULL wave in NCL then? It‘s the „zero“ of the RTZ protocol It‘s the „zero“ of the RTZ protocol Otherwise the 1-of-2 coding style is not suitable for DI: condition (C1) violated Otherwise the 1-of-2 coding style is not suitable for DI: condition (C1) violated Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 54 *

55. The Role of Glitches synchronous logic synchronous logic unproblematic (temporal masking) unproblematic (temporal masking) only clock net is problematic only clock net is problematic bundled data bundled data unproblematic (temporal masking) unproblematic (temporal masking) control path (Muller pipeline) is problematic control path (Muller pipeline) is problematic QDI QDI glitch may trigger completion detection glitch may trigger completion detection glitch may upset memory state => in general need DI implementation! glitch may upset memory state => in general need DI implementation! Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 55 *

56. Efficiency vs. Assumptions timing assumptions make life easier (simpler design process, lower area,…) timing assumptions make life easier (simpler design process, lower area,…) examples: examples: „state“ abstraction in sync. design „state“ abstraction in sync. design glitch insensitivity of sync design/BD glitch insensitivity of sync design/BD single-rail coding in bundled data single-rail coding in bundled data isochronic fork assumption in QDI isochronic fork assumption in QDI however: watch out, assumptions compromize robustness! however: watch out, assumptions compromize robustness! Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 56

57. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 57 Power saving by multirail one-of-n-coding one-of-n-coding in combination with 4-phase (RTZ) fulfills coding requirements in combination with 4-phase (RTZ) fulfills coding requirements two transitions per ld(n) bit two transitions per ld(n) bit wider bus => fewer transitions trade area for power saving wider bus => fewer transitions trade area for power saving n-of-n and 1-of-n are the extremes; the whole solution space is k-of-n n-of-n and 1-of-n are the extremes; the whole solution space is k-of-n code00000001001001001000 data(j,k)NULL00011011

58. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 58 The top 10 for async. consume power only when needed consume power only when needed achieve average case performance achieve average case performance high intrinsic robustness (PVT, faults,…) high intrinsic robustness (PVT, faults,…) low EMI emission low EMI emission easy modular composition easy modular composition metastability has time to resolve metastability has time to resolve avoid clock distribution problems avoid clock distribution problems exploit concurrence more gracefully exploit concurrence more gracefully intellectual challenge intellectual challenge intrinsic elegance intrinsic elegance (global synchrony does not exist anyway) (global synchrony does not exist anyway) [Al Davis, Async’94]

59. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 59 The truth … is, that just „going asynchronous“ is not beneficial, but is, that just „going asynchronous“ is not beneficial, but in certain cases in certain cases with carefully chosen method and implementation… with carefully chosen method and implementation… simple syn=> asyn conversion does NOT do the job! simple syn=> asyn conversion does NOT do the job! a mix of different protocols & timing models is required a mix of different protocols & timing models is required tuning of library cells is beneficial tuning of library cells is beneficial … asynchronous design can have crucial advantages, in real industrial problems … asynchronous design can have crucial advantages, in real industrial problems

60. Some Success Stories… CALTech CALTech world‘s first asynchronous processor (1989) world‘s first asynchronous processor (1989) LUTONIUM: most power-efficient 8051 implem. LUTONIUM: most power-efficient 8051 implem. Achronix Achronix world‘s fastest & most power-efficient FPGA world‘s fastest & most power-efficient FPGA Fulcrum Systems (now Intel) Fulcrum Systems (now Intel) fastest (240Gbit) Router on the market fastest (240Gbit) Router on the market GHz SRAM GHz SRAM ARM / Univ. Manchester ARM / Univ. Manchester ARM compatible core for Smartcards (SPA) ARM compatible core for Smartcards (SPA) Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 60

61. Related Research @ECS PhD theses: PhD theses: Diploma theses: Diploma theses: Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 61 PhD Panhofer: Self-Healing QDI logic PhD Friesenbichler: Fault-Tolerance in QDI PhD Ferringer: Asynchronous Logic in Real-Time App’s PhD Naqvi: Fault Tolerant NoC (incl. Arbiter) Improved asynchronous processor Limits of Fail-stop behavior of QDI Improved design flow for QDI Description methods for asyn Using NULL phase of QDI for on-line testing

62. Conclusion (1) The race condition for REQ can be avoided by appropriate data coding The race condition for REQ can be avoided by appropriate data coding Null Convention Logic (NCL) implements a 4-phase version of this scheme Null Convention Logic (NCL) implements a 4-phase version of this scheme Four-State Logic (FSL) implements the 2- phase version Four-State Logic (FSL) implements the 2- phase version Both NCL and FSL truly realize the closed- loop timing control, yielding high timing robustness, thus the QDI model applies. Both NCL and FSL truly realize the closed- loop timing control, yielding high timing robustness, thus the QDI model applies. The downside is that both techniques require storage cells even for combinational elements. The downside is that both techniques require storage cells even for combinational elements. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 62

63. Conclusion (2) When applied carefully, asynchronous design can exhibit considerable advantages over synchronous solutions with respect to energy consumption, speed, robustness, etc. When applied carefully, asynchronous design can exhibit considerable advantages over synchronous solutions with respect to energy consumption, speed, robustness, etc. The price is higher design complexity, lack of tools and libraries, and higher area The price is higher design complexity, lack of tools and libraries, and higher area So there is no general rule of when to prefer asynchronous solutions – it’s just an enhancement of the available design space. So there is no general rule of when to prefer asynchronous solutions – it’s just an enhancement of the available design space. Lecture "Advanced Digital Design"© A. Steininger / TU Vienna 63