1. WP13 Task 13.3.1 and 13.3.2 “Tools to facilitate detector development” STATUS of the ACTIVITIES WP13 Innovative gas detectors 16 March 2016

2. WP13 Task 13.3.1: Interfacing FE-chips specific to gas detectors to the Scalable Read-out System (SRS) Task 13.3.1AIDA 2020 Key/Partner Institutes Milestone [M36] VMM (ATLAS NSW, ESS, RD51) CERN: H. Muller, E. Oliveri Milestone [M36] GEMROC AGH Krakow: B. Mindur CERN: E. Oliveri Milestone [M36] Timepix3 (LC-TPC) University of Bonn: K. Desch, J. Kaminski FE chips and SRS 2

3. Soon available VMM2 chips (about 100) bought specifically for VMM/SRS developments FE chips and SRS 3 New design from A. Rusu DCARD: New design finalized. In production Design (schematics, layout,…) in progress on OCx NIM MODULE with HDMI mezzanine for APV or VMMx frontend VMMx FEC DCARD SRS Hybrid SRS Readout Electronics for VMM 128 (hardware) Design of the new SRS Hybrid with wire bonding finalized. OCx: Optical Alternative to FEC

4. ALICE FoCal (Tzukuba) VMM2 setup: Tests with detector Important support form the ATLAS NSW team (G. Iakovidis) FE chips and SRS 4 ROOT data file Charge Spectrum (without clustering) at different thresholds Control and DAQ software developed by ATALS NSW VMMx Running setup in our CERN laboratory (GDD/RD51) SRS Readout Electronics for VMM 128 (laboratory setup  on detector tests)

5. FE chips and SRS 5 Technical discussion between CERN, AGH and eicSys concluded. 100 GEMROC chips ordered using AIDA2020 resources Delivery: End of March GEMROC

6. FE chips and SRS 6 https://indico.cern.ch/event/496113/session/2/contribution/11/a ttachments/1241018/1824951/ATCA-SRS-GEMROC.pdf Intermediate Interface CARD (keeping the AGH hybrid) Final Hybrid Integration between the ATCA-SRS and the standard SRS Data Acquisition and Analysis tools (APV25).. GEMROC First Step

7. FE chips and SRS 7 Transfer between CERN and UBONN agreed between the institutes. “The budget changes will be formally approved by the Governing Board at the Annual meeting at DESY in June, but provided that both CERN and UBONN agree to this inter-beneficiary transfer (which I presume is the case), this will be just a formality.” S. Stavrev Timepix3

8. FE chips and SRS 8 -Interface board between Timepix-3 chip carriers and SRS Front-End-Card (FEC) will be developed. -Dedicated FPGA code for the FEC FPGAs to provide all basic readout and control functionality. - PC-based control code. The required EU contribution will be spent for 12 months of a PhD student (i.e. 6 FTE-months). To be considered as a partial support to the full project -Student already working (learning FPGA-Programming using the example of the SRS Timepix-1 readout) in the Timepix3 project -Pre-Financing not excluded if needed Timepix3

9. From AIDA Kick-Off Meeting FE chips and SRS 9 today No USE of AIDA resources until now (spending for vmm3, hybrids and DCARD production expected soon) About 16k from AIDA for chip production. Transfer from CERN to UBONN ongoing Resources

10. FE chips and SRS 10 SRS/FE ASICs Summary VMM SRS readout electronics for VMM existing (even if in limited number). New designs ongoing or finalized and part of them in procurement/production. Laboratory setup for VMM standalone or on detector ready. ATLAS NSW control, daq and analysis available for testing purposes. GEMROC Involvement of eicSys in the AGH/CERN partnership. Procurement of new chips done. Design ongoing of intermediate card (proof of concept toward a new hybrid) to interface AGH hybrid with SRS DCARD (VMM) and with an alternative (higher speed) transmission technology (to be exploited). Timepix3 Transfer from CERN to UBONN almost finalized (Desy meeting). PHD students focused in the FPGA coding for the Timepix3 readout (based on SRS-Timepix1) Use of AIDA2020 resources expected soon Use of AIDA2020 resources started (chips) AIDA2020 resources to be transferred to UBONN

11. WP13 Task 13.3.2: Development of cheap, standard MPGD dedicated laboratory instruments Task 13.3.2Ref. Institute/Person Deliverable [M24] High Voltage Power Supply for MPGD CERN: H. Muller, E. Oliveri; CEA: P. Colas Wigner: D. Varga; INFN Trieste: S. Dalla Torre (Floating) Pico ammeter CERN: H. Muller, E. Oliveri, INFN Trieste: S. Dalla Torre, S. Levorato; Wigner: D. Varga Signal Processing CERN: H. Muller, E. Oliveri Monitoring and Control Unit CERN: F. Brunbauer, F. Resnati, H. Muller, E. Oliveri Regeneration Gas System CEA: P. Colas Instrumentation 11 With updates from the previous meeting

12. Instr.1: Compact HV for MPGD [Deliverable – M24] Instrumentation 12 Control and Monitoring Software Voltages Currents Remote control of the main HV power supply and of the monitoring unit (ARDUINO based) for Voltage/Current readings. Outcomes from the commissioning on the actual prototype: AVD operation with Triple GEM Stable and reliable. Single channel current monitoring to be improved. Two different circuits tested. Aim: sensitivity to (sub-)nA radiation induced currents. Noise induced by the micro controller to be reduced. New design on-going with better decoupling of microcontroller and AVD AVD (Active Voltage Divider) Suitable for multistage MPGDs Arduino-based Monitoring unit Active Voltage Divider

13. Instr.1: Compact HV for MPGD [Deliverable – M24] Instrumentation 13 Next in the to do list: -Improve and validate the current reading capabilities - Decoupling (noise) the microcontroller - New case compatible with NIM-crate …and …most important: -Commissioning (induced discharges) of the operation of the e-fuse circuit to decouple detectors sectors in case of discharges and shorts. Next Commissioning/Validation Active Voltage Divider

14. APIC: Charge Preamplifier – Shaper Amplifier Chain CERN Instrumentation 14 New prototype ready New features: -preamp moved from custom (ALICE EMCAL preamp development H. Muller) to commercially available devices. -Two selectable shaping time (fast and slow) -Internally battery powering + recharging -Voltage regulated gain … keeping as in the previous version … -effective discharge protection input circuit -Two output voltages with opposite polarity -Internal Calibration Pulse…etc.etc. Successful Preliminary tests on large (about 1x0.5 m2) micromegas (T2DM2 experiment) with 5cm drift. Signal from the mesh. custom Chips commercially available APIC: C. Preamp/Shaper

15. Instrumentation 15 Fast (real-time, oscilloscope) low current measurements Anode charge-up in resistive Micromegas and its quenching effect on spark development, M.Chefdeville, Vienna Conference 2016 https://indico.cern.ch/event/391665/session/24/contribution/20 5/attachments/1230092/1803859/chefdeville.pdf Current reading capabilities (fA/pA) already proved in the non floating configuration Now focused on: -fast reading (real time – oscilloscope readout – detector transients studies) -Floating configuration (exploiting battery + PV panels or floating DC-DC with insulated dig/an I/O). FemtoBox: femto-ammeter et al.

16. Instrumentation 16 No USE of AIDA resources until now because we can cover the R&D phase via other resources. AIDA2020 support has been kept for final proto, engineering phase and to facilitate the dissemination in the community (not exclusive for the devices shown in this status report) Updates from the previous meeting Still in prototyping phase

17. FE chips and SRS 17 Instrumentation Summary… everything still in the R&D/Prototyping phase… Active Voltage Divider (High Voltage for multi electrodes MPGDs) Validation tests ongoing. Optimization/Upgrades of the single channel current reading and of the monitoring units are foreseen. Validation of e-fuse and protection circuits as a next step. Charge sensitive preamplifier & Shaper (APIC) New design with additional feature completed and prototype available. Replacement of custom components with commercially available ones. Close to final version. Femtobox Exploiting the fast reading for detector transient studies Moving towards floating/insulated solution for currents reading at HV. With progresses from the previous meeting + … not discussed today but in this subtask….. instrumentation available from partners (INFN Trieste – floating pico- ammeter as an example) and in advanced stages and/or less critical (as control/monitoring station – microcontroller- based – MoCoS/CERN) have to be considered in the context of the future phases (engineering and dissemination).