1. Diode in Digital Logic Design Section 3.1-3.3

2. Schedule #DateDayTopicSection 1 1/14TuesdayDiagnostic Test L 1/14Tuesday Lab protocol, cleaning procedure, Linus/Cadence intro 2 1/16Thursday Fundamental concepts from Electric Circuits 31/21TuesdayBasic device physics2.1 L1/21Tuesday I-V characteristics of a diode (Simulation) 4 1/23Thursday Drift/Diffusion current 5 1/28TuesdayPhysics of PN junction diode2.2-2.3 L 1/28TuesdayI-V Curve of a diode2.3 6 1/30Thursday Diode models, application of diodes in digital logic,review 3.1-3.3 (Highlights) 7 2/4Tuesday Test #1 L 2/4TuesdayDiode Logic 8 2/6ThursdayClass Canceled!

3. Outline Review Diode Model Applications of Diodes in Digital Logic –OR2 –AND2

4. Different ways of Crossing PN Junction np=n i 2 Diffusion Majority carriers cross the pn junction via diffusion (because you have the gradient) Minority carriers cross the pn junction via drift( because you have the E, not the gradient) Drift

5. Reverse Biased Diode Reverse: Connect the + terminal to the n side. Depletion region widens. Therefore, stronger E. Minority carrier to cross the PN junction easily through drift. Current is composed mostly of drift current contributed by minority carriers. n p to the left and p n to the right. Current from n side to p side, the current is negative. E

6. Forward Biased Diode Depletion region shrinks due to charges from the battery. The electric field is weaker. Majority carrier can cross via diffusion; Greater diffusion current. Current flows from P side to N side

7. I S =Reverse Saturation=leakage current

8. Diode Models (Exponential model) (Ideal model) (Constant voltage model)

9. Choosing a Diode Model Use the ideal model to develop a quick, rough understanding of a circuit. If the ideal model is not adequate, uses the constant voltage model, which is sufficient for most cases. Occasionally, we will use the exponential model

10. Ideal Model of a Diode (exponential model) (ideal model) An ideal diode will turn on even for the slightest forward bias voltage. (VD≥0) An ideal diode will turn off even for the slightest reverse bias voltage. (VD<0)

11. Behavior of Ideal Diode Ideal diode: V anode >V cathode : Diode is on V anode <V cathode : Diode is off An ideal current experieincing V anode =V cathode, carries no current

12. I/V Characteristics An Open—can’t get a current to flow. A short--can’t get a V to develop across a diode. A diode V anode >V cathode : Diode is on V anode <V cathode : Diode is off An ideal current experieincing V anode =V cathode, carries no current In practice, consider a slightly positive or negative voltage to determine the response of a diode.

13. Example 1: An OR Gate Realized By Diodes Assume that “1”=3 V “0”=0 V Assume “ideal” diode “0”=0 V

14. Exercise 1: An OR Gate Realized By Diodes Assume that “1”=3 V “0”=0 V Assume “ideal” diode “1”=3V “0”=3 V What is Vout?

15. Exercise 2: An OR Gate Realized By Diodes Assume that “1”=3 V “0”=0 V Assume “ideal” diode “1”=3V What is Vout?

16. Analysis of an OR Gate Observations: 1.If D1 is on, VA=VOUT and VOUT=“1” 2.If D2 is on, VB=VOUT and VOUT=“1”. 3.VOUT is 0 if and only if D1 and D2 are “0” This is an OR gate. Logic 1=3 V Logic 0=0V

17. Cadence Simulation of an OR Gate VA=3 V VB=3 V VOUT=2.459 V≈3V

18. Cadence Simulation of an OR Gate VA=3 V VB=0 V VOUT=2.424 V≈3V

19. Cadence Simulation of an OR Gate VA=0 V VB=0 V VOUT=0 V

20. If VD is less than VD, On, the diode behaves like an open circuit. The diode will behave like an open circuit for VD=V D,on Constant Voltage Model

21. Cadence Simulation of an OR Gate VA=3 V VB=0 V VOUT=2.424 V Constant voltage model: 3V-0.6V=2.4 V If we assume a turn on voltage of 0.6 V, we are not off by too much.

22. Grid Control

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24. In Class Exercise What kind of gate is this? Please assume ideal diode model.

25. Cadence Simulation of an AND Gate VA=3 V VB=3 V VOUT=3 V

26. In Class Exercise Assume that VA=“1”=3V, VB=“0”=0V Please assume constant voltage model. What is the output voltage?

27. Cadence Simulation of an AND Gate VA=3 V VB=0 V VOUT=0.575 V