1. CSNSM Orsay Micro-Electronics Groups Associated P. Barrillon, S. Blin, S. Callier, S. Conforti, F. Dulucq, J. Fleury, C. de La Taille, G. Martin- Chassard, L. Raux, N. Seguin-Moreau, V. Tocut + Wei Wei from IHEP Beijing

2. LAL 2 oct 08 C. de La Taille - XFEL meeting 2 Microelectronics at in2p3 Large force of microelectronics experienced engineers (~40) Expertise in detectors, connectics, chip design and test Experience in designing and building large detectors Common Cadence tools Actions : –Building blocks –Networking –poles

3. LAL 2 oct 08 C. de La Taille - XFEL meeting 3 Motivation for poles Continuous increase of chip complexity (SoC, 3D…) Importance of critical mass –Daily contacts and discussions between designers –Sharing of well proven blocks –Cross fertilization of different projects Creation of poles at in2p3 –OMEGA at Orsay –Strasbourg –Dipole Lyon-Clermont

4. LAL 2 oct 08 C. de La Taille - XFEL meeting 4 Mission Design of basic building blocks usable by all in2p3 labs for physics experiments Motivations –Target analog technology (0.35µm CMOS and SiGe AMS ) –Optimize ressources and competences within in2p3 –Increase visibility of in2p3 in microelectronics –reduce developpement times First results –2-3 runs /yr financed by in2p3 –Porquerolles workshop –Fruitful exchanges Club building blocks 0.35µm

5. LAL 2 oct 08 C. de La Taille - XFEL meeting 5 HARDROC Orsay Micro-Electronics Groups Associated A strong team of 10 ASIC designers… –= 20% of in2p3 designers –= 60% of department research engineers –A team with critical mass : pole created in 2007 = OMEGA –Expertise in low noise, low power high level of integration ASICs –2 designers/ project –2 projects/designer –Regular design meetings …Within an electronics departmt of 50 –Support for tests, mesaurements, PCBs… A steady production –A strong on-going R&D –Building blocks SiGe 0.35µm SKIROC MAROC 2 SPIROC ASPIC

6. LAL 2 oct 08 C. de La Taille - XFEL meeting 6 MAROC : 64 ch MAPMT chip for ATLAS lumi Complete front-end chip for 64 channels multi-anode photomultipliers –Auto-trigger on 1/3 p.e. at 10 MHz, 12 bit charge output –SiGe 0.35 µm, 12 mm2, Pd = 350mW PMF Hold signal PM 64 channels Photons Variable Gain Preamp. Variable Slow Shaper 20-100 ns Bipolar Fast Shaper Unipolar Fast Shaper Gain correction 64*6bits 3 discris thresholds (3*12 bits) Multiplexed Analog charge output LUCID S&H 3 DACs 12 bits 80 MHz encoder 64 Wilkinson 12 bit ADC 64 trigger outputs (to FPGA) Multiplexed Digital charge output 64 inputs S&H

7. LAL 2 oct 08 C. de La Taille - XFEL meeting 7 Active board pictures MAROC side Lattice side 64 ch PMT MAROC2 chip bounded at CERN

8. LAL 2 oct 08 C. de La Taille - XFEL meeting 8 MAROC Efficiency curves

9. LAL 2 oct 08 C. de La Taille - XFEL meeting 9 ATLAS at LHC

10. LAL 2 oct 08 C. de La Taille - XFEL meeting 10 ILC Challenges for electronics Requirements for electronics –Large dynamic range (15 bits) –Auto-trigger on ½ MIP –On chip zero suppress –Front-end embedded in detector –Ultra-low power : («25µW/ch ) –10 8 channels –Compactness « Tracker electronics with calorimetric performance » No chip = no detector !! ATLAS LAr FEB 128ch 400*500mm 1 W/ch FLC_PHY3 18ch 10*10mm 5mW/chILC : 25µW/ch W layer ASIC Ultra-low POWER is the KEY issue Si wafers

11. LAL 2 oct 08 C. de La Taille - XFEL meeting 11 The front-end ASICs : the ROC chips SPIROC Analog HCAL (SiPM) 36 ch. 32mm² June 07 HARDROC Digital HCAL (RPC, µmegas or GEMs) 64 ch. 16mm² Sept 06 SKIROC ECAL (Si PIN diode) 36 ch. 20mm² Nov 06 Technological prototypes : full scale modules (~2m) EUDET EU funding (06-09) ECAL, AHCAL, DHCAL B=5T

12. LAL 2 oct 08 C. de La Taille - XFEL meeting 12 SPIROC : Si PM Integrated Read Out Chip Internal input 8-bit DAC (0-5V) for individual SiPM gain adjustment Energy measurement : 14 bits –2 gains (1-10) + 12 bit ADC 1 pe  2000 pe –Variable shaping time from 50ns to 100ns –pe/noise ratio : 11 Auto-trigger on 1/3 pe (50fC) –pe/noise ratio on trigger channel : 24 –Fast shaper : ~10ns –Auto-Trigger on ½ pe Time measurement : –12-bit Bunch Crossing ID –12 bit TDC step~100 ps Analog memory for time and charge measurement : depth = 16 Low consumption : ~25µW per channel (in power pulsing mode) Individually addressable calibration injection capacitance Embedded bandgap for voltage references Embedded 10 bit DAC for trigger threshold and gain selection Multiplexed analog output for physics prototype DAQ 4k internal memory and Daisy chain readout

13. LAL 2 oct 08 C. de La Taille - XFEL meeting 13 DAQ ASIC Chip ID register 8 bits gain Trigger discri Output Wilkinson ADC Discri output gain Trigger discri Output Wilkinson ADC Discri output..… OR36 EndRamp (Discri ADC Wilkinson) 36 TM (Discri trigger) ValGain (low gain or high Gain) ExtSigmaTM (OR36) Channel 1 Channel 0 ValDimGray 12 bits … Acquisition readout Conversion ADC + Ecriture RAM RAM FlagTDC ValDimGray 12 8 ChipID Hit channel register 16 x 36 x 1 bits TDC ramp StartRampTDC BCID 16 x 8 bits ADC ramp Startrampb (wilkinson ramp) 16 ValidHoldAnalogb RazRangN 16 ReadMesureb Rstb Clk40MHz SlowClock StartAcqt StartConvDAQb StartReadOut NoTrig RamFull TransmitOn OutSerie EndReadOut Chipsat

14. LAL 2 oct 08 C. de La Taille - XFEL meeting 14 SPIROC performance Good analog performance –Single photo-electron/noise = 8 –Auto-trigger with good uniformity –Complex chip : many more measurements needed

15. LAL 2 oct 08 C. de La Taille - XFEL meeting 15 New club 130nm for tracking and 3D Networking : club 130nm created at VLSI workshop –Target common technology with CERN or other labs : IBM 130nm with CERN, Chartered 130nm (IBM compatible) 3D consortium : CPPM, IPHC, OMEGA-LAL, LPNHE –Complementarity –Task sharing –Coordination IN2P3 Recommendation : participate to 3D effort in a coherent, coordinated and funded way.

16. LAL 2 oct 08 C. de La Taille - XFEL meeting 16 3D technology Increasing integration density, mixing technologies Wafer thinning to <50 µm Minimization of interconnects Large industrial demand –Processors, image sensors… ©A. Klumpp (IZM)

17. LAL 2 oct 08 C. de La Taille - XFEL meeting 17 Major Markets for 3D [R. Yarema FNAL] Pixel arrays for imaging Pixel arrays with sensors and readout are well suited to 3D integration since signal processing can be placed close to the sensor. Current 2D approaches cannot handle the data rate needed for high speed imaging. Memory All major memory manufactures are working on 3D memory stacks. Significant cost reductions can be expected for large memory devices. The cost of 3D can be significantly less than going to a deeper technology node. Microprocessors A major bottleneck is access time between CPU and the memory. Memory caches are used as an interface but the area required is significant. Initial applications for 3D will use Logic to Memory, and Logic to Logic stacking. (Samsung)

18. LAL 2 oct 08 C. de La Taille - XFEL meeting 18 3D technologies Wafer stacking KGD Dice/test Die to Wafer Wafer to Wafer bonding –- must have same size wafers –- Less material handling but lower overall yield Die to Wafer bonding - Permits use of different size Wafers - Lends itself to using KGD (Known Good Die) for higher yields Wafer to Wafer

19. LAL 2 oct 08 C. de La Taille - XFEL meeting 19 ICV : Inter-Chip vias Processes « via first » and « via last » Diameters : 1 µm to 50 µm Aspect ratio ~10 Hole etching and chip thinning Via formation with W-plugs. Face to face or die up connections. 2.5 Ohm/per via (including SLID).

20. LAL 2 oct 08 C. de La Taille - XFEL meeting 20 Complete back end of line (BEOL) processing by adding Cu metal layers and top Cu metal (0.8 um) 6 um Cu Tezzaron 3D process [R. Yarema]

21. LAL 2 oct 08 C. de La Taille - XFEL meeting 21 Flip 2 nd wafer on top of first wafer. Bond second wafer to first wafer using Cu-Cu thermo-compression bond. Example: bonding identical wafers CuCu bond 12um Thin second wafer to about 12um to expose super via. Add metallization to back of 2 nd wafer for bump bond or wire bond. OR Add Cu to back of 2 nd wafer to bond 2 nd wafer to 3 rd wafer Flip 3 rd wafer Bond 3 nd wafer to 2 rd wafer. Thin 3 rd wafer to expose super via. Add final passivation and metal for pads Cu for wafer bond to 3 rd layer Face to face Face to back Tezzaron 3D process

22. LAL 2 oct 08 C. de La Taille - XFEL meeting 22 Conclusion A real move towards “smart sensors” micro-electronics getting closer to detector –Unavoidable with increase of channels number –Cost reduction Backend more and more integrated –Integration of ADC –Signal processing –Loading of parameters Coming up : 3D integration 4-side abuttable sensors