1. Computer Organization By Dr. M. Khamis

2. Computer Organization The course is aimed at designing the different computer components (circuits) and connecting these components in a way to achieve the goals of a specific architectures. Computer (hardware) consists of processor, memory and I/O units. Processor itself consists of Arithmetic Logic Unit (ALU) and Control unit. All the above units are designed using primitive logic circuits.

3. Course Objectives Understanding the basic Laws of Boolean algebra. Designing and using the basic logic devices. Understanding the operation of the main computer units and their design. Interconnecting the various computer units to achieve the specific architecture. Presenting the attributes of the different architectures. Programming specific architecture using its instruction set (machine instruction). Explaining the Interaction between Computer hardware and the operating system.

4. Course outline The course will consist of two parts: The first part is Logic design: in which the primitive components, by which the different devices are designed, are presented. The second part is intended for interconnecting the components presented in first part in a way to build a logical system (computer organization).

5. Part 1: Logic Design Introduction to number systems and arithmetic operations in binary system. Combinational circuits: Logic Gates (AND, OR, NOT, NOR, NAND and XOR), in this regards we will give the truth tables and symbols for each. Laws of Boolean algebra, deriving logical expression and simplification. Karnaugh maps and its use for simplification. half and full adders and binary coded decimal adders

6. Part 1: Logic Design devices include: Decoder. Encoder. Multiplexers/ De-multiplexer. Comparator. Sequential circuits include : Flip/Flops and counter Design Mealy and MOORE machines.

7. Part 2: Computer Organization chapter 3: computer system chapter 7: Input/output chapter 8: Operating System Support. chapter 9: Computer Arithmetic chapter 10: Instruction Sets. chapter 11: :Instruction Sets: Addressing Modes and Format. chapter 12: CPU structure chapter 16 : Control Unit chapter 17: Micro Programmed Control Unit.

8. N UMBERS AND B OOLEAN A LGEBRA Author: Abhinav Bhatele Revised By: Dr. M. Khamis FAll 2008

9. N UMBER SYSTEMS To get started, we’ll discuss one of the fundamental concepts underlying digital computer design: Deep down inside, computers work with just 1s and 0s. Computers use voltages to represent information. In modern CPUs the voltage is usually limited to 1.6-1.8V to minimize power consumption. It’s convenient for us to translate these analog voltages into the discrete, or digital, values 1 and 0. But how can binary system be useful for anything? First, we’ll see how to represent numbers with just 1s and 0s. Then we’ll introduce special operations for computing with 1s and 0s, by treating them as the logical values “true” and “false.” Volts 1.8 0 1 0 June 10th, 2008 8 Number Systems and Boolean Algebra

10. T ODAY ’ S LECTURE Number systems Review of binary number representation How to convert between binary and decimal representations Octal and Hex representations Basic boolean operations AND, OR and NOT The idea of “Truth Table” Boolean functions and expressions Truth table for Boolean expressions June 10th, 2008 9 Number Systems and Boolean Algebra

11. D ECIMAL REVIEW Numbers consist of a bunch of digits, each with a weight These weights are all powers of the base, which is 10. We can rewrite this: To find the decimal value of a number, multiply each digit by its weight and sum the products. (1 x 10 2 ) + (6 x 10 1 ) + (2 x 10 0 ) + (3 x 10 -1 ) + (7 x 10 -2 ) + (5 x 10 -3 ) = 162.375 June 10th, 2008 10 Number Systems and Boolean Algebra

12. C ONVERTING BINARY TO DECIMAL We can use the same trick to convert binary, or base 2, numbers to decimal. This time, the weights are powers of 2. Example: 1101.01 in binary The decimal value is: (1 x 2 3 ) + (1 x 2 2 ) + (0 x 2 1 ) + (1 x 2 0 ) + (0 x 2 -1 ) + (1 x 2 -2 ) = 8+ 4+ 0+ 1+ 0+ 0.25= 13.25 June 10th, 2008 11 Number Systems and Boolean Algebra

13. C ONVERTING DECIMAL TO BINARY To convert a decimal integer into binary, keep dividing by 2 until the quotient is 0. Collect the remainders in reverse order. To convert a fraction, keep multiplying the fractional part by 2 until it becomes 0. Collect the integer parts in forward order. Example: 162.375: So, 162 10 = 10100010 2 162 / 2= 81rem 0 81 / 2= 40rem 1 40 / 2= 20rem 0 20 / 2= 10rem 0 10 / 2= 5rem 0 5 / 2= 2rem 1 2 / 2= 1rem 0 1 / 2= 0rem 1 June 10th, 2008 12 Number Systems and Boolean Algebra

14. W HY DOES THIS WORK ? This works for converting from decimal to any base Why? Think about converting 162.375 from decimal to decimal. Each division strips off the rightmost digit (the remainder). The quotient represents the remaining digits in the number. 162 / 10= 16rem 2 16 / 10= 1rem 6 1 / 10= 0rem 1 June 10th, 2008 13 Number Systems and Boolean Algebra

15. B ASE 16 IS USEFUL TOO The hexadecimal system uses 16 digits: 0 1 2 3 4 5 6 7 8 9 A B C D E F You can convert between base 10 and base 16 using techniques like the ones we just showed for converting between decimal and binary. For our purposes, base 16 is most useful as a “shorthand” notation for binary numbers. Since 16 = 2 4, one hexadecimal digit is equivalent to 4 binary digits. It’s often easier to work with a number like B4 instead of 10110100. Hex is frequently used to specify things like 32-bit IP addresses and 24-bit colors. June 10th, 2008 14 Number Systems and Boolean Algebra

16. B INARY AND HEXADECIMAL CONVERSIONS Converting from hexadecimal to binary is easy: just replace each hex digit with its equivalent 4-bit binary sequence. To convert from binary to hex, make groups of 4 bits, starting from the binary point. Add 0s to the ends of the number if needed. Then, just convert each bit group to its corresponding hex digit. 261 16 = 2 6 1 =001001100001 10110100 2 =10110100 = B 4 June 10th, 2008 15 Number Systems and Boolean Algebra

17. 2’ s complement Binary number can be represented using sign and magnitude. If N bits are used to represent the number, then the last bit is used to hold the sign of the number while the other (N-1) bits are used to represent the value. 0 is used for +ve sign and 1 is used for -ve sign. To get the 2’s complement for any number follow the following two steps: 1. Convert each bit in the value into its complement (1 to 0 and vice versa) 2. Add 1 to the result of step 1.

18. Binary addition & subtraction If the number is +ve keep it in sign and magnitude form, otherwise represent the number (magnitude only) using its 2’s complement. Add the binary numbers in the ordinary way as the decimal numbers. The addition in decimal makes carry 1 for the next digit for each 10 collected in the sum, and the reset which will be less than 10 is left as result of the addition of corresponding bits. This operation continues until adding all of the corresponding bits in the numbers.

19. Binary addition & subtraction (Continued) The addition in binary is exactly the same as decimal with only one difference, which is, carry 1 is taken for the next digit for each 2 collected in the sum, and the reset which is less than 2 is left as result of the addition of corresponding bits. The addition is continued for all bits including the sign bit, and in order to get correct answer the number must be represented in enough number of bits. Any carry after the sign bit is discarded. The value of the negative result is represented in the 2’s complement (i.e. the actual value is the 2’s complement of the result once again).

20. N UMBER S YSTEMS S UMMARY Computers are binary devices. We’re forced to think in terms of base 2. Today we learned how to convert numbers between binary, decimal and hexadecimal. Also, we have seen: We use 0 and 1 as abstractions for analog voltages. We showed how to represent numbers using just these two signals. Next we’ll introduce special operations for binary values and show how those correspond to circuits. June 10th, 2008 19 Number Systems and Boolean Algebra

21. B OOLEAN O PERATIONS So far, we’ve talked about how arbitrary numbers can be represented using just the two binary values 1 and 0. Now we’ll interpret voltages as the logical values “true” and “false” instead. We’ll show: How logical functions can be defined for expressing computations How to build circuits that implement our functions in hardware June 10th, 2008 20 Number Systems and Boolean Algebra

22. B ASIC B OOLEAN OPERATIONS There are three basic operations for logical values. AND (product) of two inputs OR (sum) of two inputs NOT (complement) on one input xy, or x  yx + yx’ Operation: Expression: Truth table: June 10th, 2008 21 Number Systems and Boolean Algebra

23. B OOLEAN EXPRESSIONS We can use these basic operations to form more complex expressions: f(x,y,z) = (x + y’)z + x’ Some terminology and notation: f is the name of the function. (x,y,z) are the input variables, each representing 1 or 0. Listing the inputs is optional, but sometimes helpful. A literal is any occurrence of an input variable or its complement. The function above has four literals: x, y’, z, and x’. Precedences are important, but not too difficult. NOT has the highest precedence, followed by AND, and then OR. Fully parenthesized, the function above would be kind of messy: f(x,y,z) = (((x +(y’))z) + x’) June 10th, 2008 22 Number Systems and Boolean Algebra

24. T RUTH TABLES A truth table shows all possible inputs and outputs of a function. Remember that each input variable represents either 1 or 0. Because there are only a finite number of values (1 and 0), truth tables themselves are finite. A function with n variables has 2 n possible combinations of inputs. Inputs are listed in binary order—in this example, from 000 to 111. f(0,0,0)= (0 + 1)0 + 1= 1 f(0,0,1)= (0 + 1)1 + 1= 1 f(0,1,0)= (0 + 0)0 + 1= 1 f(0,1,1)= (0 + 0)1 + 1= 1 f(1,0,0)= (1 + 1)0 + 0= 0 f(1,0,1)= (1 + 1)1 + 0= 1 f(1,1,0)= (1 + 0)0 + 0= 0 f(1,1,1)= (1 + 0)1 + 0= 1 f(x,y,z) = (x + y’)z + x’ June 10th, 2008 23 Number Systems and Boolean Algebra

25. P RIMITIVE LOGIC GATES Each of our basic operations can be implemented in hardware using a primitive logic gate. Symbols for each of the logic gates are shown below. These gates output the product, sum or complement of their inputs. Logic gate: AND (product) of two inputs OR (sum) of two inputs NOT (complement) on one input xy, or x  yx + yx’ Operation: Expression: June 10th, 2008 24 Number Systems and Boolean Algebra

26. E XPRESSIONS AND CIRCUITS Any Boolean expression can be converted into a circuit by combining basic gates in a relatively straightforward way. The diagram below shows the inputs and outputs of each gate. The precedences are explicit in a circuit. Clearly, we have to make sure that the hardware does operations in the right order ! (x + y’)z + x’ June 10th, 2008 25 Number Systems and Boolean Algebra

27. C IRCUIT ANALYSIS SUMMARY After finding the circuit inputs and outputs, you can come up with either an expression or a truth table to describe what the circuit does. You can easily convert between expressions and truth tables. Find the circuit’s inputs and outputs Find a Boolean expression for the circuit Find a truth table for the circuit June 10th, 2008 26 Number Systems and Boolean Algebra

28. B OOLEAN OPERATIONS SUMMARY We can interpret high or low voltage as representing true or false. A variable whose value can be either 1 or 0 is called a Boolean variable. AND, OR, and NOT are the basic Boolean operations. We can express Boolean functions with either an expression or a truth table. Every Boolean expression can be converted to a circuit. Next, we’ll look at how Boolean algebra can help simplify expressions, which in turn will lead to simpler circuits. June 10th, 2008 27 Number Systems and Boolean Algebra

29. B OOLEAN ALGEBRA Last time we talked about Boolean functions, Boolean expressions, and truth tables. Now we’ll learn how to how use Boolean algebra to simplify Booleans expressions. Last time, we saw this expression and converted it to a circuit: (x + y’)z + x’ Can we make this circuit “better”? Cheaper: fewer gates Faster: fewer delays from inputs to outputs June 10th, 2008 28 Number Systems and Boolean Algebra

30. E XPRESSION SIMPLIFICATION Normal mathematical expressions can be simplified using the laws of algebra For binary systems, we can use Boolean algebra, which is superficially similar to regular algebra There are many differences, due to having only two values (0 and 1) to work with having a complement operation the OR operation is not the same as addition June 10th, 2008 29 Number Systems and Boolean Algebra

31. F ORMAL DEFINITION OF B OOLEAN ALGEBRA A Boolean algebra requires A set of elements B, which needs at least two elements (0 and 1) Two binary (two-argument) operations OR and AND A unary (one-argument) operation NOT The axioms below must always be true (textbook, p. 42) The magenta axioms deal with the complement operation Blue axioms (especially 15) are different from regular algebra June 10th, 2008 30 Number Systems and Boolean Algebra

32. C OMMENTS ON THE AXIOMS The associative laws show that there is no ambiguity about a term such as x + y + z or xyz, so we can introduce multiple-input primitive gates: In the next table: The left and right columns of axioms are duals (i.e. exchange all ANDs with ORs, and 0s with 1s) The dual of any equation is always true June 10th, 2008 31 Number Systems and Boolean Algebra

33. A RE THESE AXIOMS FOR REAL ? We can show that these axioms are valid, given the definitions of AND, OR and NOT The first 11 axioms are easy to see from these truth tables alone. For example, x + x’ = 1 because of the middle two lines below (where y = x’) June 10th, 2008 32 Number Systems and Boolean Algebra

34. P ROVING THE REST OF THE AXIOMS We can make up truth tables to prove (both parts of) DeMorgan’s law For (x + y)’ = x’y’, we can make truth tables for (x + y)’ and for x’y’ In each table, the columns on the left (x and y) are the inputs. The columns on the right are outputs. In this case, we only care about the columns in blue. The other “outputs” are just to help us find the blue columns. Since both of the columns in blue are the same, this shows that (x + y)’ and x’y’ are equivalent June 10th, 2008 33 Number Systems and Boolean Algebra

35. S IMPLIFICATION WITH AXIOMS We can now start doing some simplifications x’y’ + xyz + x’y = x’(y’ + y) + xyz[ Distributive; x’y’ + x’y = x’(y’ + y) ] = x’  1 + xyz[ Axiom 7; y’ + y = 1 ] = x’ + xyz[ Axiom 2; x’  1 = x’ ] = (x’ + x)(x’ + yz)[ Distributive ] = 1  (x’ + yz)[ Axiom 7; x’ + x = 1 ] = x’ + yz[ Axiom 2 ] June 10th, 2008 34 Number Systems and Boolean Algebra

36. L ET ’ S COMPARE THE RESULTING CIRCUITS Here are two different but equivalent circuits. In general the one with fewer gates is “better”: It costs less to build It requires less power But we had to do some work to find the second form June 10th, 2008 35 Number Systems and Boolean Algebra

37. S OME MORE LAWS Here are some more useful laws. Notice the duals again! We can prove these laws by either Making truth tables: Using the axioms: x + x’y= (x + x’)(x + y)[ Distributive ] = 1  (x + y)[ x + x’ = 1 ] = x + y[ Axiom 3 ] June 10th, 2008 36 Number Systems and Boolean Algebra

38. T HE COMPLEMENT OF A FUNCTION The complement of a function always outputs 0 where the original function outputted 1, and 1 where the original produced 0. In a truth table, we can just exchange 0s and 1s in the output column(s) f(x,y,z)= x(y’z’ + yz) June 10th, 2008 37 Number Systems and Boolean Algebra

39. C OMPLEMENTING A FUNCTION ALGEBRAICALLY You can get thr complement of a function by one of 2-ways; 1. You can use DeMorgan’s law to keep “pushing” the complements inwards 2. You can also take the dual of the function, and then complement each literal If f(x,y,z) = x(y’z’ + yz)… … the dual of f is x + (y’ + z’)(y + z)… … then complementing each literal gives x’ + (y + z)(y’ + z’)… … so f’(x,y,z) = x’ + (y + z)(y’ + z’) f(x,y,z)= x(y’z’ + yz) f’(x,y,z)= ( x(y’z’ + yz) )’[ complement both sides ] = x’ + (y’z’ + yz)’[ because (xy)’ = x’ + y’ ] = x’ + (y’z’)’ (yz)’[ because (x + y)’ = x’ y’ ] = x’ + (y + z)(y’ + z’)[ because (xy)’ = x’ + y’, twice] June 10th, 2008 38 Number Systems and Boolean Algebra

40. S UMMARY SO FAR So far: A bunch of Boolean algebra trickery for simplifying expressions and circuits The algebra guarantees us that the simplified circuit is equivalent to the original one Next: Introducing some standard forms and terminology An alternative simplification method We’ll start using all this stuff to build and analyze bigger, more useful, circuits June 10th, 2008 39 Number Systems and Boolean Algebra

41. Parity Checking Parity checking is used to check the correctness or erroneous of data. Circuit used to raise 1 on its output when its input data contain even number of 1’s is called even parity circuit, otherwise it called odd parity circuit. Parity checking is used with memory to ensure the read data is exactly as written one or otherwise, it interrupts the main processor. Also, it is used within the modem to ensure the correct arrival of the received data.

42. Parity Checking with the Main Memory Parity RAM Data RAM Parity cct To interrut processor

43. How is parity circuits detect the error? The table depicts the expected output of the parity checking during reading data (yellow circuit). Note that the output will be always1 when memory is defected, otherwise, it will be 0. Original Data Output of parity in case of Correctfaulty data Oddoddeven Evenoddeven

44. Design parity checking for 3-inputs For sake of simplicity 3-inputs are considered. The truth table will be as shown. The output (F) of the even parity circuit is 1 when the number of the 1’s in the inputs are even. F= xyz’ + xy’z + x’yz + x’y’z’ (Draw the corresponding circuit for the above logic expression to get the odd parity circuit for 3-inputs) xyzF 1110 1101 1011 1000 0111 0100 0010 0001

45. How to add binary numbers Consider adding two 1-bit binary numbers x and y 0+0 = 0 0+1 = 1 1+0 = 1 1+1 = 10 Carry is x AND y Sum is x XOR y The circuit to compute this is called a half-adder xyCarrySum 0000 0101 1001 1110

46. The half-adder Sum = x XOR y Carry = x AND y

47. Using half adders We can then use a half-adder to compute the sum of two Boolean numbers 1 1 0 0 + 1 1 1 0 010? 001

48. How to fix this We need to create an adder that can take a carry bit as an additional input Inputs: x, y, carry in Outputs: sum, carry out This is called a full adder Will add x and y with a half-adder Will add the sum of that to the carry in xyccarrysum 11111 11010 10110 10001 01110 01001 00101 00000

49. The full adder The “HA” boxes are half-adders HA X Y S C X Y S C x y c X Y S C X Y S C x y c c s

50. The full adder The full circuitry of the full adder x y s c c

51. Adding bigger binary numbers (4 bits parallel binary adder) This design is available with IC 7483

52. Seven Segment Example Seven-segment display used to display binary values visually To do so it needs a driver to convert from 4 bit binary to 7-segments output.

53. d ’ output of the driver (decoder to 7 segment)

54. Simplified expression of “ d ” Karnaugh Map Method Don ’ t cares simplify the expression a lot

55. Using decoder to 7-segment to display the output of the 4-bits adder on 7-segment All output of the decoder to 7-segments is calculated in similar way (IC 7447 performing the function of the decoder to 7-segments).

56. Adding bigger binary numbers A half adder has 4 logic gates A full adder has two half adders plus a OR gate Total of 9 logic gates To add n bit binary numbers, you need 1 HA and n-1 FAs To add 32 bit binary numbers, you need 1 HA and 31 FAs Total of 4+9*31 = 283 logic gates To add 64 bit binary numbers, you need 1 HA and 63 FAs Total of 4+9*63 = 571 logic gates

57. More about logic gates To implement a logic gate in hardware, you use a transistor Transistors are all enclosed in an “IC”, or integrated circuit The current Intel Pentium IV processors have 55 million transistors!

58. Summary: Digital Logic Basics Hardware consists of a few simple building blocks These are called logic gates AND, OR, NOT, … NAND, NOR, XOR, … Logic gates are built using transistors NOT gate can be implemented by a single transistor AND gate requires 3 transistors Transistors are the fundamental devices Pentium consists of 3 million transistors Compaq Alpha consists of 9 million transistors Now we can build chips with more than 100 million transistors

59. Basic Concepts Simple gates AND OR NOT Functionality can be expressed by a truth table A truth table lists output for each possible input combination Precedence NOT > AND > OR F = A B + A B = (A (B)) + ((A) B)

60. Basic Concepts (cont.) Additional useful gates NAND NOR XOR NAND = AND + NOT NOR = OR + NOT XOR implements exclusive- OR function NAND and NOR gates require only 2 transistors AND and OR need 3 transistors!

61. Basic Concepts (cont.) Proving NAND gate is universal NAND gate is called universal gate

62. Basic Concepts (cont.) Proving NOR gate is universal NOR gate is called universal gate

63. Logic Functions Logical functions can be expressed in several ways: Truth table Logical expressions Graphical form Example: Majority function Output is 1 whenever majority of inputs is 1 We use 3-input majority function

64. Logic Functions (cont.) 3-input majority function ABCF 0000 0010 0100 0111 1000 1011 1101 1111 Logical expression form F = A B + B C + A C

65. Logical Equivalence All three circuits implement F = A B function

66. Logical Equivalence (cont.) Proving logical equivalence of two circuits Derive the logical expression for the output of each circuit Show that these two expressions are equivalent Two ways: You can use the truth table method For every combination of inputs, if both expressions yield the same output, they are equivalent Good for logical expressions with small number of variables You can also use algebraic manipulation Need Boolean identities

67. Logical Equivalence (cont.) Derivation of logical expression from a circuit Trace from the input to output Write down intermediate logical expressions along the path

68. Logical Equivalence (cont.) Proving logical equivalence: Truth table method A BF1 = A BF3 = (A + B) (A + B) (A + B) 0 0 0 1 0 0 1 0 0 0 1 1

69. Logic Circuit Design Process A simple logic design process involves Problem specification Truth table derivation Derivation of logical expression Simplification of logical expression Implementation

70. Deriving Logical Expressions Derivation of logical expressions from truth tables sum-of-products (SOP) form product-of-sums (POS) form SOP form Write an AND term (minterms) for each input combination that produces a 1 output Write the variable if its value is 1; complement otherwise OR the AND terms to get the final expression POS form Dual of the SOP form (each literal is complemented and each OR is converted to AND and vice virsa)

71. Deriving Logical Expressions (cont.) 3-input majority function ABCF 0000 0010 0100 0111 1000 1011 1101 1111 SOP logical expression Four product terms Because there are 4 rows with a 1 output

72. Deriving Logical Expressions (cont.) 3-input majority function ABCF 0000 0010 0100 0111 1000 1011 1101 1111 POS logical expression Four sum terms Because there are 4 rows with a 0 output

73. Logical Expression Simplification Two basic methods Algebraic manipulation Use Boolean laws to simplify the expression Difficult to use Don ’ t know if you have the simplified form Karnaugh map (K-map) method Graphical method Easy to use Can be used to simplify logical expressions with a few variables

74. Algebraic Manipulation Majority function example A B C + A B C + A B C + A B C = A B C + A B C + A B C + A B C + A B C + A B C We can now simplify this expression as B C + A C + A B A difficult method to use for complex expressions Added extra

75. Karnaugh Map Method Note the order

76. Karnaugh Map Method (cont.) Simplification examples

77. Karnaugh Map Method (cont.) First and last columns/rows are adjacent

78. Karnaugh Map Method (cont.) Minimal expression depends on groupings

79. Karnaugh Map Method (cont.) No redundant groupings

80. Karnaugh Map Method (cont.) Example Seven-segment display Need to select the right LEDs to display a digit

81. Karnaugh Map Method (cont.)

82. Don ’ t cares simplify the expression a lot

83. Implementation Using NAND Gates Using NAND gates Get an equivalent expression A B + C D = A B + C D Using de Morgan ’ s law A B + C D = A B. C D Can be generalized Majority function A B + B C + AC = A B. BC. AC Idea: NAND Gates: Sum-of-Products, NOR Gates: Product-of-Sums

84. Implementation Using NAND Gates (cont.) Majority function

85. Introduction to Combinational Circuits Combinational circuits Output depends only on the current inputs Combinational circuits provide a higher level of abstraction Help in reducing design complexity Reduce chip count We look at some useful combinational circuits

86. Princess Sumaya University 4241 - Digit al Logi c Desi gn 85 / 16 B INARY D ECODER ● Black box with n input lines and 2 n output lines ● Only one output is a 1 for any given input Binary Decoder n inputs 2 n outputs

87. Princess Sumaya University 4241 - Digit al Logi c Desi gn 86 / 16 2- TO -4 B INARY D ECODER F 0 = X'Y' F 1 = X'Y F 2 = XY' F 3 = XY XY 2-to-4 Decoder X Y F0 F1 F2 F3 Note: Each output is a 2-variable minterm (X'Y', X'Y, XY' or XY)

88. Princess Sumaya University 4241 - Digit al Logi c Desi gn 87 / 16 3- TO -8 B INARY D ECODER F 1 = x'y'z xzy F 0 = x'y'z' F 2 = x'yz' F 3 = x'yz F 5 = xy'z F 4 = xy'z' F 6 = xyz' F 7 = xyz 3-to-8 Decoder X Y F0 F1 F2 F3 F4 F5 F6 F7 Z

89. Princess Sumaya University 4241 - Digit al Logi c Desi gn 88 / 16 ● Any n-variable logic function can be implemented using a single n-to-2 n decoder to generate the minterms ● OR gate forms the sum ● The output lines of the decoder corresponding to the minterms of the function are used as inputs to the OR gate ● Any combinational circuit with n inputs and m outputs can be implemented with an n-to-2 n decoder with m OR gates ● Suitable when a circuit has many outputs, and each output function is expressed with few minterms I MPLEMENTING F UNCTIONS U SING D ECODERS

90. Princess Sumaya University 4241 - Digit al Logi c Desi gn 89 / 16 I MPLEMENTING F UNCTIONS U SING D ECODERS Example: Full adder S(x, y, z) =  (1,2,4,7) C(x, y, z) =  (3,5,6,7) 3-to-8 Decode r S2S1S0S2S1S0 x y z 0123456701234567 S C

91. Princess Sumaya University 4241 - Digit al Logi c Desi gn 90 / 16 U SE TWO 3 TO 8 DECODERS TO MAKE 4 TO 16 DECODER ● Enable can also be active high ● In this example, only one decoder can be active at a time

92. Princess Sumaya University 4241 - Digit al Logi c Desi gn 91 / 16 E NCODERS ● If the a decoder's output code has fewer bits than the input code, the device is usually called an encoder. ● e.g. 2 n -to-n ● The simplest encoder is a 2 n -to-n binary encoder ● One of 2 n inputs = 1 ● Output is an n-bit binary number............ 2 n inputs n outputs Binary encoder

93. Princess Sumaya University 4241 - Digit al Logi c Desi gn 92 / 16 8- TO -3 B INARY E NCODER At any one time, only one input line has a value of 1. 00 00000100101 00000010110 00000001111 I0I1I2I3I4I5I6I7I0I1I2I3I4I5I6I7 y 0 = I 1 + I 3 + I 5 + I 7 y 1 = I 2 + I 3 + I 6 + I 7 y 2 = I 4 + I 5 + I 6 + I 7

94. Princess Sumaya University 4241 - Digit al Logi c Desi gn 93 / 16 8- TO -3 P RIORITY E NCODER ● What if more than one input line has a value of 1? ● Ignore “lower priority” inputs ● Idle indicates that no input is a 1 ● Note that polarity of Idle is opposite from Table 4-8 in Mano

95. Princess Sumaya University 4241 - Digit al Logi c Desi gn 94 / 16 P RIORITY E NCODER (8 TO 3 E NCODER ) ● Assign priorities to the inputs ● When more than one input are asserted, the output generates the code of the input with the highest priority ● Priority Encoder : H7=I7 (Highest Priority) H6=I6.I7’ H5=I5.I6’.I7’ H4=I4.I5’.I6’.I7’ H3=I3.I4’.I5’.I6’.I7’ H2=I2.I3’.I4’.I5’.I6’.I7’ H1=I1. I2’.I3’.I4’.I5’.I6’.I7’ H0=I0.I1’. I2’.I3’.I4’.I5’.I6’.I7’ IDLE= I0’.I1’. I2’.I3’.I4’.I5’.I6’.I7’ ● Encoder Y0 = I1 + I3 + I5 + I7 Y1 = I2 + I3 + I6 + I7 Y2 = I4 + I5 + I6 + I7 Y1 Y2 Y0 IDLE I1 I2 I3Y1 Y2I4 I5 I6 I0 Y0 I7 Binary encoder I1 I2 I3 I4 I5 I6 I0 I7 Priority Circuit H1 H2 H3 H4 H5 H6 H0 H7 IDLE I1 I2 I3 I4 I5 I6 I0 I7 Priority Encoder

96. Princess Sumaya University 4241 - Digit al Logi c Desi gn 95 / 16 H OMEWORK Mano4-27 4-28 1. Design a 3-bit binary-to-seven-segment decoder using only a 3-to-8 line decoder and OR gates. Label the inputs x, y, and z (with z being the least significant bit) and label the outputs a, b, c, d, e, f, and g.

97. Princess Sumaya University 4241 - Digit al Logi c Desi gn 96 / 16 S UMMARY ● Decoders allow for generation of a single binary output from an input binary code ● For an n-input binary decoder there are 2 n outputs ● Decoders are widely used in storage devices (e.g. memories) to allow extension ● Encoders can be used for data compression ● Priority encoders rank inputs and encode the highest priority input