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COE 202 Introduction to Verilog Computer Engineering Department College of Computer Sciences and Engineering King Fahd University of Petroleum and Minerals.

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Presentation on theme: "COE 202 Introduction to Verilog Computer Engineering Department College of Computer Sciences and Engineering King Fahd University of Petroleum and Minerals."— Presentation transcript:

1 COE 202 Introduction to Verilog Computer Engineering Department College of Computer Sciences and Engineering King Fahd University of Petroleum and Minerals

2 Outline  Always block  Procedural Assignment  If Statements  Case Statements  Comparator  Arithmetic & Logic Unit  Multiplexor  Encoder  Priority Encoder  Decoder

3 Always Block  always blocks are procedural blocks that contain sequential statements.  Syntax  always @(sensitivity list) begin  end  sensitivity list prevents the always block from executing again until another change occurs on a signal in the sensitivity list.  Level type  always @(a or b or c)  Edge type  always @(posedge clock)  always @(negedge clock)

4 Procedural Assignment  Assignments inside an always block are called procedural assignments  Can only be used within an always block  Two types : blocking assignment and nonblocking assignment. Basic syntax :  [variable-name] = [expression] ; // blocking assignment  [variable-name] <= [expression] ; // nonblocking assignment  In a blocking assignment, the expression is evaluated and then assigned to the variable immediately, before execution of the next statement (the assignment thus "blocks" the execution of other statements). It behaves like the normal variable assignment in the C language.

5 Procedural Assignment  In a nonblocking assignment, the evaluated expression is assigned at the end of the always block (the assignment thus does not block the execution of other statements).  The basic rule of thumb is:  Use blocking assignments for a combinational circuit.  Use nonblocking assignments for a sequential circuit  There are two types of variables in Verilog:  wire (all outputs of assign statements must be wire)  reg (all outputs modified in always blocks must be reg)  if-else and case statement are only in always block.

6 If Statements if (expression) begin...procedural statements... end else if (expression) begin...statements... end...more else if blocks else begin...statements... end module ALU #(parameter n=8) (output reg [n-1:0] c, input [1:0] s, input [n-1:0] a, b); always @(s or a or b) begin if (s==2'b00) c = a + b; else if (s==2'b01) c = a - b; else if (s==2'b10) c = a & b; else c = a | b; end endmodule

7 Case Statements case (expression) case_choice1: begin...statements... end case_choice2: begin...statements... end...more case choices blocks... default: begin...statements... end endcase module ALU2 #(parameter n=8) (output reg [n-1:0] c, input [1:0] s, input [n-1:0] a, b); always @(s or a or b) begin case (s) 2'b00: c = a + b; 2'b01: c = a - b; 2'b10: c = a & b; default: c = a | b; endcase end endmodule

8 Full Adder module fadd2 (output reg S, Cout, input A, B, Cin); always @(A or B or Cin) begin S = (A ^ B ^ Cin); Cout = (A & B) | (A & Cin) | (B & Cin); end endmodule

9 Comparator module comp #(parameter width=32) (input [width-1:0] A, B, output A_gt_B, A_lt_B, A_eq_B); assign A_gt_B = (A>B); assign A_lt_B = (A<B); assign A_eq_B = (A==B); endmodule

10 Comparator module comp2 #(parameter width=2) (input [width-1:0] A, B, output reg A_gt_B, A_lt_B, A_eq_B); always @(A, B) begin A_gt_B = 0; A_lt_B = 0; A_eq_B = 0; if (A == B) A_eq_B = 1; else if (A > B) A_gt_B = 1; else A_lt_B = 1; end endmodule

11 Arithmetic Unit module arithmetic #(parameter width=8) (input [width-1:0] A, B, input [1:0] Sel, output reg [width-1:0] Y, output reg Cout); always @(A or B or Sel) begin case (Sel) 2'b 00 : {Cout,Y} = A+B; 2'b 01 : {Cout,Y} = A-B; 2'b 10 : {Cout,Y} = A+1; 2'b 11 : {Cout,Y} = A-1; default: begin Cout=0; Y=0; end endcase end endmodule

12 Logic Unit module logic #(parameter width=4) (input [width-1:0] A, B, input [2:0] Sel, output reg [width-1:0] Y); always @(A or B or Sel) begin case (Sel) 3'b 000 : Y = A & B; // A and B 3'b 001 : Y = A | B; // A or B 3'b 010 : Y = A ^ B; // A xor B 3'b 011 : Y = ~A; // 1’s complement of A 3'b 100 : Y = ~(A & B); // A nand B 3'b 101 : Y = ~(A | B); // A nor B default : Y = 0; endcase end endmodule

13 2x1 Multiplexer Method 1 module mux2x1 (input b, c, select, output a); assign a = (select ? b : c); endmodule Method 2 module mux2x1 (input b, c, select, output reg a); always@(select or b or c) begin if (select) a=b; else a=c; end endmodule Method 3 module mux2x1 (input b, c, select, output reg a); always@(select or b or c) begin case (select) 1’b1: a=b; 1’b0: a=c; endcase end endmodule

14 Encoder module encoder (output reg [2:0] Code, input [7:0] Data); always @(Data) if (Data==8'b00000001) Code = 0; else if (Data==8'b00000010) Code = 1; else if (Data==8'b00000100) Code = 2; else if (Data==8'b00001000) Code = 3; else if (Data==8'b00010000) Code = 4; else if (Data==8'b00100000) Code = 5; else if (Data==8'b01000000) Code = 6; else if (Data==8'b10000000) Code = 7; else Code = 'bx; endmodule

15 Priority Encoder module priority_encoder (output reg [2:0] Code, output valid_data, input [7:0] Data); assign valid_data = | Data; always @(Data) if (Data[7]) Code = 7; else if (Data[6]) Code = 6; else if (Data[5]) Code = 5; else if (Data[4]) Code = 4; else if (Data[3]) Code = 3; else if (Data[2]) Code = 2; else if (Data[1]) Code = 1; else if (Data[0]) Code = 0; else Code = 'bx; endmodule

16 Priority Encoder module priority_encoder2 (output reg [2:0] Code, output valid_data, input [7:0] Data); assign valid_data = | Data; always @(Data) case (Data) 8'b1xxxxxxx : Code = 7; 8'b01xxxxxx : Code = 6; 8'b001xxxxx : Code = 5; 8'b0001xxxx : Code = 4; 8'b00001xxx : Code = 3; 8'b000001xx : Code = 2; 8'b0000001x : Code = 1;8'b00000001 : Code = 0; default: Code = 'bx; endcase endmodule

17 Decoder module decoder (output reg [7:0] Data, input [2:0] Code); always @(Code) if (Code == 0 ) Data= 8'b00000001; else if (Code == 1 ) Data= 8'b00000010; else if (Code == 2 ) Data= 8'b00000100; else if (Code == 3 ) Data= 8'b00001000; else if (Code == 4 ) Data= 8'b00010000; else if (Code == 5 ) Data= 8'b00100000; else if (Code == 6 ) Data= 8'b01000000; else if (Code == 7 ) Data= 8'b10000000; else Data = 'bx; endmodule

18 Seven Segment Display Decoder module Seven_Segment_Display (output reg [6:0] Display, input [3:0] BCD); parameter BLANK = 7’b111_1111; parameter ZERO= 7’b000_0001; //abc_defg parameter ONE= 7’b100_1111; parameter TWO= 7’b001_0010; parameter THREE= 7’b000_0110; parameter FOUR= 7’b100_1100; parameter FIVE= 7’b010_0100; parameter SIX= 7’b010_0000; parameter SEVEN= 7’b000_1111; parameter EIGHT= 7’b000_0000; parameter NINE= 7’b000_0100; always @(BCD) case (BCD) 0: Display = ZERO; 1: Display = ONE; 2: Display = TWO; 3: Display = THREE; 4: Display = FOUR; 5 : Display = FIVE; 6: Display = SIX; 7: Display = SEVEN; 8: Display = EIGHT; 9: Display = NINE; default: DISPLAY = BLANK; endcase endmodule

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