1. Status report 2011/7/28 Atsushi Nukariya

2. Progress Progresses are as follows. 1. FPGA -> Analyze data from FPGA, and some revise point is found. 2. Software -> It works correctly.

3. FPGA -1- ・ Test on implementation mode. -> Data generator in FPGA generates data. -> It works correctly. -> Input pulse on chip. -> Some data is seen, but some revise point is found.

4. FPGA -2- ・ Input pulse form is as follows. -> Input this pulse to capacitor which converts voltage to current. 3us 13us 400mV

5. FPGA -3- ・ Delay value is set to 1. This is minimum value which FPGA can set. -> This value determines integration time. Delay

6. FPGA -4- ・ Voltage is input on chip D, channel 0. -> Data which info value is 0x03 or 0x07, should be seen.(Details can be seen in status report at 28 th June, 2011. ) CHIPCHANNELFIFORESERVED 2bit 3bit1bit 0 0 0 00101 1

7. FPGA -5- ・ Some result is shown. http://www.cns.s.u-tokyo.ac.jp/~nukariya/GEMFE2/20110722-1.dat -> Serious mistakes is found. -> Busy flag is output except for chip D. ・ However, data from chip D, channel 0 and FIFO A shows some result.

8. FPGA -6- ・ Increase amplitude. http://www.cns.s.u-tokyo.ac.jp/~nukariya/GEMFE2/20110722-2.dat -> Some value is bigger than previous one. -> However FPGA has serious problem, consider this topic after revising FPGA.

9. FPGA -7- ・ Readout order is mistake. Board Chip A Chip B Chip C Chip D 1 2 3 4 5 6 7 8 Board Chip A Chip B Chip C Chip D 1 5 2 6 3 7 4 8

10. FPGA -8- ・ In addition to change readout order, readout part from chip is renewal. -> Previous design can be seen at status report 15 th July, 2011. ・ New design has advantage as follows. * Read data from chip with parallel processing. -> Speed up. * Forget about chip control when process data in FPGA. -> Control point is decreased and Flexibility is increased.

11. FPGA -9- ・ New design is as follows. -> 4 FIFOs, 4 chip controllers and multiplexer are added. FIFO Chip Controller Chip Controller Chip Controller Chip Controller MUX SiTCP FIFO

12. FPGA -10- ・ Chip controller follows state machine. * STOP -> No processing is occurred. * READY -> Prepare for data transmit. * RCLK_RISE -> Readout data from chip. * NEXT_DATA -> Prepare for next data. * CHANNEL_END -> Procedure for empty flag is detected. * CYCLE_END_READY -> Prepare to finish 1 cycle. * CYCLE_END -> Prepare to stop data transmit. ・ In chip controller, info is added. ・ When state is CYCLE_END, 0x7fffff is written to FIFO.

13. FPGA -11- ・ State machine diagram is as follows.

14. FPGA -12- ・ Simulation is conducted. -> Data comes from data generator in FPGA.

15. FPGA -13- ・ Info outputs without problem. ・ 0x7fffff is output correctly. ・ Implementation test isn ’ t conducted yet.

16. Source code FPGA http://www.cns.s.u-tokyo.ac.jp/~nukariya/GEMFE2/src/gemfe2_fpga/ Debug Software http://www.cns.s.u-tokyo.ac.jp/~nukariya/GEMFE2/src/gemfe2_debug_software/ Script http://www.cns.s.u-tokyo.ac.jp/~nukariya/GEMFE2/src/gemfe2_scripts/ Image Processing Software http://www.cns.s.u-tokyo.ac.jp/~nukariya/GEMFE2/src/gemfe2_software/