1. HCAL Modules -First Ideas Mathias ReineckeHCAL – MPI meetingJan. 2007 1.Motivation 2.Mechanical Constraints 3.HCAL Base Unit (HBU) 4.Light Calibration System Further development of the HCAL-Group‘s ideas.

2. HCAL and FEB Mathias ReineckeHCAL – MPI meetingJan. 2007 FEB can help in: Analog / Digital Circuit and System Design Circuit Simulation PCB Design Software (µC, Device Drivers, Control SW – C, C++, Labview) Support during Commissioning (grounding, shielding, EMC)

3. Mechanical Constraints Mathias ReineckeHCAL – MPI meetingJan. 2007 HCAL Half-Sector with 38 layers HCAL Base-Unit (HBU): - each HBU is 12 tiles (36 cm) deep - always 6 HBUs in a row cover the full sector length - 2 or 3 HBU-rows of different widths cover a layer -Height: ~2.6 cm per layer - Width B increases with 1.02 cm per layer - Tile Size 3 x 3 cm² => 76000 Tiles (Half Sector) Smallest layer: 74 x 220 cm² Largest layer : 96 x 220 cm² Layer Concentrator

4. Mechanical Constraints Mathias ReineckeHCAL – MPI meetingJan. 2007 HCAL: 2 x 8 Sectors 2,432,000 Tiles Requirements for a HCAL Base-Unit (HBU) from the Barrel‘s mechanics: -As large as possible (assembly time) -As thin as possible (barrel diameter) -Easy de-/installation of single units (repair) -If possible: not larger than 43cm (PCB assembly, unit construction, stability) -Rail System needed (Sector Orientation) -Minimize dead area -Number of SiPM inputs per ASIC ??? Request of LAL: Multiples of 18

5. How to Fill the Sector‘s Layers Mathias ReineckeHCAL – MPI meetingJan. 2007 Depths of all HBUs: 12 tiles (36 cm), 6 HBUs = 216cm Sector layer widths: 24 tiles (72cm) to 33 tiles (99cm) Layer Width [tiles] HBU width [tiles] Tiles per HBU Unused HBU inputs for ASIC with 54 inputs72 inputs64 inputs 24 12+12 8+8+8 144 96 18 12 - 48 32 25 12+13 8+8+9 156 108 6-6- 60 36 20 276+10+1112042248 28 6+10+12 8+9+11 72 132 36 30 - 12 56 60 3310+12+1214418-48 Needed HBU widths to fill all sector layers: 54‘er HBUs of: 8, 9, 11, 12 and 13 tiles width or 72‘er HBUs of: 6, 8, 10, 11 and 12 tiles width. Switch off unused inputs !!

6. Tiles in the HBU Mathias ReineckeHCAL – MPI meetingJan. 2007 Standard Tile: 30 x 30 x 3 mm³ Tile Alignment Pins ~ 2mm height SiPM Carrier Mechanics Tile: HBU Interconnection and Rail System mounting 6mm bolt with M3 thread inside

7. HBU – How could it look like ? Mathias ReineckeHCAL – MPI meetingJan. 2007 Rail System 2mm/1mm Reflector Foil 100µm Polyimide Foil 100µm PCB 1mm Bolt with inner M3 thread welded to bottom plate SiPM Tile 3mm HBU Interface 1mm gap Bottom Plate 600µm ASIC LQFP-144 1.4mm high Top Plate 300µm Component Area: 1.7 mm high HBU height: 6.9mm (6.0mm without covers => absorber) Steel Plate

8. HBU height – Component Area Mathias ReineckeHCAL – MPI meetingJan. 2007 There is still room for a few 100µm. -HBU Interconnection (1.3mm): -ASIC (1.4mm): 1mm: max 100 pins -Blocking Capacitor (1.1mm): 0.8mm: max 4.7µF -SiPM Solder Pins (1.5mm): 1mm possible? -Rail System (2mm) is 2mm sufficient?

9. HBU Insertion (Top View) Mathias ReineckeHCAL – MPI meetingJan. 2007 Rail System PCB ASIC Tile HBU Interconnection: 1.Close Mechanical Tabs 2.Close Electrical Conn. 3.Push into Sector Layer 4.Repeat 1-3: Six HBUs in a row. Steel Absorber

10. Light Calibration System Mathias ReineckeHCAL – MPI meetingJan. 2007 Use ‚Distance‘ of Single-Photon Peaks for calibration (LED light output level not critical), couple LED light into the Tile Alignment Pins: LED One LED per tile : No fibers needed. One LED per HBU : No fibers between modules (HBUs) PCB Reflector Foil

11. Temperature / Power Dissipation Mathias ReineckeHCAL – MPI meetingJan. 2007 From P. Göttlicher No. channels: 1000 / m² Train: 1ms length in 5Hz rate Pow. Diss.: 40µW / channel (25µW ASIC, 15µW HV) Time constant of heat effects:  = ~6 days, 0.33K (z=0)  Current consumption:  3 A/plane (during train)

12. Conclusions Mathias ReineckeHCAL – MPI meetingJan. 2007 -Very first idea about how things could look like. -Nothing is fixed. -Concept is basis for further discussions.