1. SHAKTI PROCESSORS RAHUL BODDUNA RISE LAB, IIT MADRAS rahul.bodduna@gmail.com

2. SHAKTI SERIES C Class microcontrollers – Fault Tolerant Variant I Class processors M Class processors S Class processors H Class processors

3. I Class Processor -Features Based on RISC-V ISA Dual Fetch out-of-order issue using merged register file approach. Parameterized pipeline and Issue Queue. CAM based speculative load store unit. Inter-functional unit bypass network. Tournament Branch Predictor.

4. Design Pipeline Stages 1.FETCH 2.DECODE 3.MAP 4.SELECT AND GRANT 5.DATA READ AND DRIVE 6.EXECUTE 7.COMMIT

5. Instruction Issue and Bypass Network Instruction Issue: – Age based Issue – Position Based Issue Bypass Network

6. CAM based Load Store Unit Each memory access instruction is allotted an entry in one of LS queues. The value from the store is forwarded in case of address match. Alias bit is set in case of wrong speculation and pipeline is flushed at the time of commit.

7. Verification Environment AAPG Initialiased memory Instructions ISS Processor Match ? I-Cache D-Cache no modify Automatic Assembly Program Generator(AAPG) generates random assembly instruction – written in python. Instruction Set Simulator(ISS) – functional equivalent of processor in C. Register dump after every instruction is matched against each other for verification.

8. IPC for AAPG Test Cases IPC variation based on issue queue size.

9. Using Bypass network….

10. Frequency recorded 65 nm UMCIP Standard cell library with operating conditions 1.32 V supply voltage and 110 0F is used.

11. Dhrystone Results

12. Fault Tolerant Variant of C Class 32-bit 5 stage pipeline with branch prediction. Supports all integer instructions. Resilient against hard and soft errors. Tolerate single bit error from fetch stage to writeback stage. Tolerate one ALU failure in the execution unit.

13. Single Bit Error Mitigation. Hamming Codes are used for Single Error Correction(SEC) and Double Error Detection(DEC) techniques to mitigate errors in Memories and Registers. SEC-DED logic is placed in the design after inter stage buffer (ISB) and before the combinational logic.

14. Fault Tolerance in ALU Design. FunctionInstructions handled of RISC-V ISA ft_add_subLUI, AUIPC, ADD, ADDI, SUBAddition/Substraction related ft_adderLoad & store, Jump, BranchEffective Address Calculation

15. FunctionInstructions Handled of RISC-V ISARemarks ft_multiplierMUL, MULH, MULHSU, MULHUMultiplication Instructions