1. Introduction to Microprocessor

2. Micro-Operations A computer executes a program Fetch/execute cycle Each cycle has a number of steps Called micro-operations Each step does very little Atomic operation of CPU

3. Types of Micro-operation Transfer data between registers Transfer data from register to external Transfer data from external to register Perform arithmetic or logical ops

4. Structure - Top Level Computer Main Memory Input Output Systems Interconnection Peripherals Communication lines Central Processing Unit Computer

5. Structure - The CPU Computer Arithmetic and Login Unit Control Unit Internal CPU Interconnection Registers CPU I/O Memory System Bus CPU

6. Basic Elements of Processor ALU Registers Internal data pahs External data paths Control Unit

7. Organization of A Microprocessor-based System (Computer) CPU – Central Processing Unit Memory —ROM – Read Only Memory —RAM – Random Access Memory I/O —Keyboard —Display Device Clock – Square Wave Oscillator (Timing) System Bus

8. Microprocessor (CPU) —Programmable integrated device (silicon chip) that has computing & decision making capabilities —Communicates & operates in binary numbers 0 & 1, called bits —Has a fixed set of instructions in the form of binary patterns – machine language —Difficult for humans to remember machine language – each instruction is represented using abbreviated names (mnemonics)

9. Memory —Symbolic representation Word: no. of bits micro-P recognizes and processes at a time ( 4 - 64bit ). Instruction: combination of bit patterns with specific meaning known to micro-P. Program: Set of all instructions. address Word length 1 word instruction 2 word instruction

10. I/O —Microprocessor’s connection to the outside world –Input: Keyboard, mouse –Output: Monitor, printer

11. System Bus – wires connecting memory & I/O to microprocessor —Address Bus –Unidirectional –Identifying peripheral or memory location —Data Bus –Bidirectional –Transferring data —Control Bus –Synchronization signals –Timing signals –Control signal

12. Actions performed by microprocessor: —CPU – Memory —CPU – I/O —Data Processing –Arithmetic operations –Logical operations —Control –Jump –Interrupts

13. Basic Concepts of Microprocessors Differences between: —Microcomputer – a computer with a microprocessor as its CPU. Includes memory, I/O etc. —Microprocessor – silicon chip which includes ALU, register circuits & control circuits —Microcontroller – silicon chip which includes microprocessor, memory & I/O in a single package.

14. Differences between: —High level language —Assembly language —Machine language

15. Fetch - 4 Registers Memory Address Register (MAR) —Connected to address bus —Specifies address for read or write op Memory Buffer Register (MBR) —Connected to data bus —Holds data to write or last data read Program Counter (PC) —Holds address of next instruction to be fetched Instruction Register (IR) —Holds last instruction fetched

16. Functions of Control Unit Sequencing —Causing the CPU to step through a series of micro-operations Execution —Causing the performance of each micro-op This is done using Control Signals

17. Control Signals Clock —One micro-instruction (or set of parallel micro- instructions) per clock cycle Instruction register —Op-code for current instruction —Determines which micro-instructions are performed Flags —State of CPU —Results of previous operations From control bus —Interrupts —Acknowledgements

18. Model of Control Unit

19. Fetch Sequence Address of next instruction is in PC Address (MAR) is placed on address bus Control unit issues READ command Result (data from memory) appears on data bus Data from data bus copied into MBR PC incremented by 1 (in parallel with data fetch from memory) Data (instruction) moved from MBR to IR MBR is now free for further data fetches

20. First Generation – Vacuum tubes (1940) 1ENIAC 1.Electronic Numerical Integrator And Computer 2.Eckert and Mauchy of University of Pennsylvania 3.Started 1943 and Finished 1946

21. ENIAC features 1.Decimal (not binary) 2.20 accumulators of 10 digits 3.Programmed manually by switches 4.18,000 vacuum tubes 5.30 tons 6.15,000 square feet 7.140 kW power consumption 8.5,000 additions per second

22. Electronic Numerical Integrator and Computer (ENIAC)Computer

23. Second Generation – Transistor (1956) Transistor was Invented 1947 at Bell Labs William Shockley et al. –Replaced vacuum tubes –Smaller –Cheaper –Less heat dissipation –Solid State device –Made from Silicon (Sand) Digital Equipment Corporation (DEC)

24. Third Generation – IC (1963) From Magnetic Memory to Semiconductor Memory Integrated Circuits used. In the beginning magnetic core memories were used. Later they were replaced by semiconductor memories (RAM & ROM).

25. Fourth generation - VLSI 1.CPU in a chip - microprocessor Personal computers 1.IBM PC 2.Apple 3.commodore Intel (integrated electronics)

26. Fifth generation – (1980) The fifth generation was intended to convey the system as being a leap beyond existing machines Computers based on artificial intelligence are available Introduced ULSI (Ultra Large Scale Integration) technology Supercomputer Vector computer

27. 4004 First microprocessor (1971) For Busicom calculator Characteristics 10 m process 2300 transistors PMOS Technology 400 – 800 kHz 4-bit microprocessor 4KB Main Memory 45 instructions 50 KIPS 16-pin DIP package

28. 8008 8-bit version of 4004 (1972) Characteristics 10 m process 3500 transistors 500 – 800 kHz 8-bit word size 18-pin DIP package 16 KB main memory 48 instructions NMOS Technology

29. 8080 16-bit address bus (1974) Used in Altair computer Characteristics 6 m process 4500 transistors 2 MHz 40-pin DIP package 8-bit microprocessor 64 KB main memory 48 instructions NMOS Technology 500Kinstructions/sec

30. 10-01-2011ES C263 Microprocessor Programming and Interfacing 30 3  m process 29k transistors 5-10 MHz 40-pin DIP package 1.5 µm process 134k transistors

31. 10-01-2011ES C263 Microprocessor Programming and Interfacing 31 1-0.6µm process 1.2M transistors 168-pin PGA 1.5-1 µm process 275k transistors 100-pin PGA

32. 10-01-2011ES C263 Microprocessor Programming and Interfacing 32 0.8-0.35 µm process 3.2M transistors 296-pin PGA

33. 10-01-2011ES C263 Microprocessor Programming and Interfacing 33 180 – 90 nm process 42-125M transistors 1.4-3.4 GHz 32-bit word size 478-pin PGA

34. 34 Intel® Core™ i7-975 processor Extreme Edition Launch date: June 2009 3.33 GHz core speed Up to 3.6 GHz with Intel® Turbo Boost Technology 4 cores and 8 processing threads with Intel® Hyper-Threading Technology 8 MB Intel® Smart Cache 3 Channels DDR3 1066 MHz memory 45nm manufacturing process technology

35. 35 Intel® Core™ i7-980X processor Extreme Edition Launch Date: March 2010 3.33 GHz core speed Up to 3.6 GHz with Intel® Turbo Boost Technology 6 cores and 12 processing threads with Intel® Hyper-Threading Technology 12 MB Intel® Smart Cache 3 Channels DDR3 1066 MHz memory 32nm manufacturing process technology

36. Intel 8085 Microprocessor Microprocessor consists of: —Control unit: control microprocessor operations. —ALU: performs data processing function. —Registers: provide storage internal to CPU. —Interrupts —Internal data bus

37. Intel 8085 CPU Block Diagram ALU

38. Intel 8085 Pin Configuration

39. Registers —General Purpose Registers –B, C, D, E, H & L (8 bit registers) –Can be used singly –Or can be used as 16 bit register pairs +BC, DE, HL –H & L can be used as a data pointer (holds memory address) —Special Purpose Registers –Accumulator (8 bit register) +Store 8 bit data +Store the result of an operation +Store 8 bit data during I/O transfer

40. Flag Register —8 bit register – shows the status of the microprocessor before/after an operation —S (sign flag), Z (zero flag), AC (auxillary carry flag), P (parity flag) & CY (carry flag) —Sign Flag –Used for indicating the sign of the data in the accumulator –The sign flag is set if negative (1 – negative) –The sign flag is reset if positive (0 – positive) D7D6D5D4D3D2D1D0 SZXACXPXCY

41. Zero Flag —Is set if result obtained after an operation is 0 —Is set following an increment or decrement operation of that register Carry Flag —Is set if there is a carry or borrow from arithmetic operation 10110011 + 01001101 --------------- 1 00000000 1011 0101 + 0110 1100 --------------- Carry 1 0010 0001 1011 0101 - 1100 1100 --------------- Borrow 1 1110 1001

42. Auxillary Carry Flag —Is set if there is a carry out of bit 3 Parity Flag —Is set if parity is even —Is cleared if parity is odd 1011 0101 + 0110 1100 --------------- 1 0010 0001

43. 16 – Bit Registers —Program Counter –A pointer to the next instruction to be executed –Contains the 16-bit memory address of the next instruction –Updated after processor has fetched the instruction —Stack Pointer –Stack – an area in memory in which temporary info is stored –Stack – FILO (First In Last Out) basis –Holds the address of the top of the stack

44. Non Programmable Registers Instruction Register & Decoder —Instruction is stored in IR after fetched by processor —Decoder decodes instruction in IR Internal Clock generator —3.125 MHz internally —6.25 MHz externally

45.  Microprocessor 8085 pin Configuration Intel 8085 is an 8 bit,. It is a 40 pin IC package fabricated on a single LSI. Description of various pins: 1.A 8 -A 15 (Output): These are address bus and are used for the MSB of the memory address. or I/O address. 1.AD o -AD 7 (Input / Output): These are time multiplexed address / data bus i.e. they serve dual purpose. They are used for the LSB of the memory address. or I/O address during the first clock cycle of the machine cycle. They are used as data during the second and third clock cycle of the machine cycle. 1.ALE (Output): It is an address latch enable signal. It goes high during the first clock cycle of the machine cycle and enables the lower 8 bits of the address to be latched either into the memory or external latch.

47. 4.IO/M (Output): It is a status signal which distinguishes whether the address is for memory or I/O. When it goes low the address in the address bus is for the memory. 5.S o,S 1 (Output): These are status signals sent by the microprocessor to distinguish the various types of operation given. 1.0,0 - Halt 2.0,1 - write 3.1,0 - Read 4.1,1 - Fetch ___ 6.RD(Output): It is a signal to control READ operation. When it is low the selected memory or I/O device is read.

48. 7.WR (Output): It is a signal to control WRITE operation. When it is low the data on the data bus is written into the selected memory or I/O device. 8.READY (Input) It is used by the microprocessor to check whether the peripherals is ready to transfer data or not. If READY is high the peripheral is ready. If it is low MP waits for the signal to goes high. 9.HOLD (Input): It indicates that another device is requesting the use of the address and data bus. Having received a HOLD request the MP relinquishes the use of the buses as soon as current machine cycle is completed. 10.HLDA (output): It is a signal for HOLD acknowledgement. It indicates that the HOLD request have been received.

49. 11.INTR (input): It is an interrupt request signal. Among interrupts it has lowest priority. When it goes high the program counter does not increment its contents. The microprocessor suspends its normal sequence of operations. After completing the instruction at hand it goes to the call instruction. The INTR line is sampled in the last state of the last machine cycle of the instruction. The microprocessor acknowledges the interrupt signal and issues INTA signal. 12.RST5.5.6.5.7.5 and TRAP (inputs): These are interrupts. When an interrupt is recognized the next instruction is executed from a fixed location in the memory as given below: 1.TRAP 0024 2.RST5.5002C 3.RST6.5 0034 4.RST7.5 003C RST 7.5,6.5.5.5 are the restart interrupts. They cause an internal restart to be automatically inserted. Each of them has a programmable mask. The TRAP has the highest priority among interrupts. It is a nonmaskable interrupts. It is unaffected by any mask or interrupt. The priority of the interrupts is in the order of TRAP(Highest), RST7.5. RST6.5, RST5.5, INTR.

50. 13.RESET IN (Input): It resets the program counter to zero. It also resets the interrupt enable and HLDA flip-flops. It does not effect any other flag or register except the instruction register, The CPU is held in reset condition as long as RESET is applied. 14.RESET OUT (Output): It indicates that the CPU is being reset. 15.X1, X2: (Input): These are terminals to be connected to an external crystal oscillator which drives an internal circuitry of the microprocessor to produce a suitable clock for the operation of microprocessor. 16.CLK : It is a clock output for user, which can be used for other digital IC’s Its frequency is same at which processor operates. 17.SID (Input) It is data line for serial input. 18.SOD (Output): it is a data line for serial output. 19.VCC: +5 Volts Supply 20.V SS : Ground Reference

51. The 8085 Machine Cycle and Bus Timings An instruction is a command given to a computer to perform a specified operation on the given data. To perform a particular task a programmer writes a sequence of instructions, called a program. Program and data are stored in the memory. The processor fetches one instruction from the memory at a time and execute it. It executes all the instructions of the program one by one and produce the final result. Instruction Cycle The necessary steps which a processor carries out to fetch an instruction and data from the memory and to execute that instruction constitute and instruction cycle. An instruction cycle consist of two steps Fetch cycle and Execute cycle. In the fetch cycle the processor fetches the instruction from the memory. The necessary steps which are carried out to get data and perform the specific operation given in the instruction constitute a execute cycle. IC = FC + EC

52. Op-code & Operand Each instruction contains two parts Operation Code (Opcode) and Operand. The first part of the instruction which specifies a task to be performed by the processor is called Opcode. The second part of the instruction is the data to be operated upon is called Operand.

53. Instruction and Data Flow Instruction Register MDR Instruction Decoder ---------------------------------- Control Program Counter MAR Memory Data Bus Memory Address Bus

54.  Addressing Modes of MP 8085 Each instruction performs an operation on the specified data called operand. An operand must be specified for an instruction to be executed. The operand may be in the general purpose register, accumulator or in a memory location. The way in which the operand is specified for an instruction is called addressing mode. Various addressing modes used in MP 8085 are: 1.Direct Addressing 2.Register Addressing 3.Register Indirect Addressing 4.Immediate Addressing. 5.Implicit Addressing  Direct addressing: In this mode of addressing the address of the operand (data) is given in the instruction itself. For example: 1.STA 2400H: Store the content of the accumulator to memory location 2400H. 2.IN 02: Read data from port C, 02 is the address of the port C of an I/O port from where data is to be read.  Register Addressing: In register addressing mode the operands are in the general purpose registers. For example: 1.MOV A,B: This instruction moves the contents of register B to register A or Accumulator. 2.ADD B: Add the contents of register B to accumulator.

55.  Register indirect addressing: In this mode of addressing the address of the operand (data) is specified by a register pair. For example: 1.LXI H, 2500H: Load HL pair with 2500H. MOV A,M : Move the contents of memory location whose address is given in HL pair to the accumulator. HLT: Stop the program. In this program MOV A,M is the example of Register Indirect addressing. 2.LXI H, 2500H: Load HL pair with 2500H. ADD M : Add the contents of memory location whose address is given in HL pair to the accumulator. HLT: Stop the program. In this program ADD,M is the example of Register Indirect addressing.  Immediate Addressing: In immediate addressing mode the operands are specified within the instruction itself. For example: 1.MVI A,05 : Move 05 in the Accumulator. 2.ADI 06 : Add 06 to the contents of the accumulator.  Implicit Addressing: There are certain instructions which operate on the content or the Accumulator directly, these instructions do not require the address of the operands. For example 1.CMA : Compliment the contents of the Accumulator. 2.RAR : Rotate the contents of the accumulator right by one bit. 3.RAL : Rotate the contents of the accumulator left by one bit.

56. The steps which MP8085 takes to fetches machine codes from the memory can be understood with the help of the command MOV C,A (4F) stored at memory location 2005H : 1.The program places the 16 bit address on the address bus. At time T1 the high order address 20H is placed on the address line A15-A8, the low order memory address 05H is placed on the data bus AD7-AD0 and the address latch signal goes high. Similarly the status signal IO/M goes low, indicating that this is memory related operation. 2.The control unit sends the control signal RD to enable the memory chip. This signal is sent out during the clock period T2, thus enabling the memory chip. The RD signal is active during two clock periods. 3.The byte from the memory location is placed on the data bus. When the memory is enabled the instruction byte (4F) is placed on the bus AD7-AD0 and transferred to the microprocessor. 4.The byte is placed in the instruction decoder of the microprocessor, and the task is carried out. The machine code 4F is decoded by the instruction decoder and the contents of the accumulator are copied into the register C. This task is performed during the period T4

57. The 8085 Machine Cycle and Bus Timings (cont…..) Example :- In MP8085 we have two machine codes 3EH ( MVI A, data) and 32H are stored at memory location 2000H and 2001H respectively. Illustrate the bus timing. Calculate the required time to execute the Opcode Fetch and Memory Read cycles and the entire instruction cycle if the clock frequency is 2 MHzs. Ans :- This instruction consists of two bytes; the first op-code and the second is the data byte. The MP reads these bytes from the memory and thus requires at least two machine cycles. The first machine cycle is the Opcode fetch and the second machine cycle is the memory read.

58. First machine cycle M1:- At T1 microprocessor places the memory address 2000H from the PC on the address bus. 20H on the A15-A8, and 00H on the bus AD7-AD0. The ALE signal goes high during T1. which is used to latch the low order address 00H to AD7-AD0. The status signals are S1 = 1, S0=1 At T2 the MP asserts the RD control signal, which enables the memory, and memory places the byte 3EH from location 2000H on the data bus. During T3 the MP places the opcode in the instruction register and disables the RD signal. The fetch cycle is completed in state T3 During T4 the instruction is decoded

59. Second machine cycle M2:- At T1 microprocessor places the memory address 2001H from the PC on the address bus. 20H on the A15-A8, and 01H on the bus AD7-AD0. The ALE signal goes high during T1. which is used to latch the low order address 00H to AD7-AD0. The status signals are S1 = 1, S0=0 At T2 the MP activates the data bus as the input bus, memory places the data byte 32H on the data bus. During T3 the MP reads and store the byte in accumulator.

60. The execution time —Clock frequency f = 2 Mz —T- state = Clock Period = 1/f = 0.5 µs —Execution time for fetch cycle = 4 X.5 = 2 µs —Execution time for Memory Read = 3 X.5 = 1.5 µs —Execution time for the instruction = 3.5 µs

61. The 8085 Machine Cycle and Bus Timings (cont…..) Example :- In MP8085 explain the machine cycle for the instruction STA 2065 (32H,65,20). The machine codes are stored at the memory locations 2010H, 2011H, 2012H. Ans :- This instruction consists of three bytes; the first op-code and the second and the third are the address of the memory location. This instruction stores the contents of the accumulator in the memory location 2065H. It consists of 4 machine cycles. 1.First machine cycle M1:- In the first machine cycle the MP places the address 2010 on the address bus and fetches the opcode 32h. It requires 4T states. 2.Second machine cycle M2:- In the second machine cycle the memory is read. The processor places the address 2011 and gets the low order byte 65H. It requires 3T states. 3.Third machine cycle M3:- The third machine cycle is also the Memory Read cycle. The processor gets the high order byte 20H from the memory location 2012. It requires 3 T states 4.Forth machine cycle M4 :- The last machine cycle is the memory write. The MP places the address of 2065H on the address bus, identifies the operation as Memory Write ( S1=0, S0=0 ). It places the contents of the accumulator on the data bus AD7-AD0 and asserts the WR signal. During the last T state the contents of the data bus are placed in memory location 2065H. It requires 3T states.

63. Instruction Set of 8085 An instruction is a command given to the computer to perform a specified operation on given data. The 8085-instructions are classified into five group: 1.Data Transfer Group 2.Arithmetic Group 3.Logical Group 4.Branch Control Group 5.I/O and Machine Control Group

64. Data Transfer Group Related with moving data from one place to another. Not be mistaken as the idea that data is literally “moved”, instead it is copied from one location to another. This particular type of instruction set does not modify data.

65. Data Transfer Group (Contd.) Instructions related with this category perform the following transfers: Load data from memory into microprocessor. Store data from the microprocessor into memory. Move data within the microprocessor. Input data to the microprocessor. Output data from the microprocessor.

66. MOV r, M. Move the content of memory location, whose address is in H-L pair, is moved to register r. MOV M, r. The content of register r is moved to the memory location addresses by H-L pair.

67. MVI r, data. Move immediate data in the register r. MVI M, data. The data is moved to memory location whose address is in H-L pair LXI rp, data (16-bits) Load the register pair with 16-bits data.

68. LDA addr. The content of the memory location, whose address is specified by the 2 nd and 3 rd bytes of the instruction; is loaded into the accumulator. STA addr. The content of accumulator is stored in the memory location whose address is specified by the 2 nd and 3 rd bytes of the instruction.

69. LHLD addr. The content of the memory location, whose address is specified by the 2 nd and 3 rd bytes of the instruction is loaded into register L, the content of next memory location is loaded into register H. SHLD addr. The content of the register L is stored in the memory location whose address is specified by the 2 nd and 3 rd bytes of the instruction, the content of register H is stored in the next memory location.

70. LDAX rp. The content of memory location, whose address is in the register pair rp, is loaded into the accumulator. STAX rp. The content of the accumulator is stored in the memory location whose address is in the register pair rp. XCHG. The contents of H-L pair are exchanged with contents of D-E pair.

71. Arithmetic Group Related with performing arithmetic operations. This particular type of instruction set modify data. The operations are:- Addition Subtraction Increment Decrement

72. ADD r. The content of register r is added to the content of the accumulator, and the sum is placed in the accumulator. ADD M. The content of the memory location addressed by H-L pair is added to the content of the accumulator. ADC r. The content of register r and carry status are added to the content of the accumulator. ADC M. The content of the memory location addressed by H-L pair and carry status are added to the content of the accumulator.

73. ADI data. The immediate data is added to the content of the accumulator. ACI data. The immediate data and the carry status are added to the content of the accumulator. DAD rp. The contents of register pair rp are added to the contents of H-L pair and the result is placed in H-L pair.

74. SUB r. The content of register r is subtracted from the content of the accumulator, and the result is placed in the accumulator. SUB M. The content of the memory location addressed by H-L pair is subtracted from the content of the accumulator. SBB r. The content of register r and carry status are subtracted from the content of the accumulator. SBB M. The content of memory location addressed by H-L pair and carry status are subtracted from the content of the accumulator.

75. SUI data. The immediate data is subtracted from the content of the accumulator. SBI data. The immediate data and carry status subtracted from the content of the accumulator. INR r. The content of register r is incremented by one. INR M. The content of memory location addressed by H-L pair is incremented by one.

76. DCR r. The content of register r is decremented by one. DCR M. The content of memory location addressed by H-L pair is decremented by one. INX rp. The content of register pair rp is incremented by one. DCX rp. The content of register pair rp is decremented by one.

77. DAA. This instruction is used in the program after ADD, ADI, ACI, ADC, etc instruction. After the execution of ADD, ADC, etc instruction the result is in hexadecimal and it is placed in the accumulator. This instruction operates on this result and gives the final result in decimal system.

78. Logical Group Instructions in this group perform AND,OR, Ex-Or operations; compare,rotate,or take complement of data in register or memory.

79. ANA r.-> ( AND register with accumulator.) It contents of register are ANDed with the content of the accumulator, and the result is placed in the accumulator. ANA M.-> (AND memory with accumulator. ) Contents of memory location addressed by H-L pair and is ANDed with the accumulator. The result is placed in accumulator.

80. ANI data (AND immediate data with accumulator ) The 2 nd byte of instruction is data, and it is ANDed with the content of the accumulator. The result is placed in accumulator. ORA r (OR) register with accumulator. Contents of registered are ORed with content of accumulator. The result is placed in the accumulator.

81. ORA M.-> (OR memory with accumulator. ) Contents of memory location addressed by H-L pair and is ORed with the accumulator. The result is placed in accumulator. ORI data (OR immediate data with accumulator ) The 2 nd byte of instruction is data, and it is ORed with the content of the accumulator. The result is placed in accumulator. CS=0 and AC=0.

82. XRA r (Ex-OR) register with accumulator. Contents of registered are Ex-ORed with content of accumulator. The result is placed in the accumulator. XRA M.-> (Ex-OR memory with accumulator. ) Contents of memory location addressed by H-L pair and is Ex-ORed with the accumulator. The result is placed in accumulator.

83. XRI data (Ex-OR immediate data with accumulator ) The 2 nd byte of instruction is data, and it is Ex-ORed with the content of the accumulator. The result is placed in accumulator. CMA (Compliment the accumulator) 1’s compliment of accumulator is obtained and result is placed in accumulator. To obtain the 1’s compliment of a binary number 1 is replaced by 0 or 0 by 1.

84. CMC (Compliment the carry status) CS flag is complimented. other flags are not affected. STC (Set carry status) Status flag CS is set to 1. Other flags are not affected.

85. CMP r. The content of register r is subtracted from the content of the accumulator and the status flags are set according to the result of the subtraction. The content of accumulator remains unchanged. CMP M. The content of memory location addressed by H-L pair is subtracted from the content of the accumulator and the status flags are set according to the result of the subtraction. The content of accumulator remains unchanged.

86. CPI data. The 2 nd byte of the instruction is data, and it is subtracted from the content of the accumulator. The status flags are set according to the result of subtraction. But the result is discarded.

87. RRC. The content of the accumulator is rotated right by one bit. The zero bit of the accumulator is moved to carry bit as well as to the seventh bit of the accumulator. RAL. The content of the accumulator is rotated left one bit through carry. The seventh bit of the accumulator is moved to carry and the carry bit is moved to the zero bit of the accumulator.

88. RRC. The content of the accumulator is rotated right one bit through carry. The zero bit of the accumulator is moved to carry bit, and the carry bit moved to seventh bit of the accumulator.

89. Branch Group The instructions of this group change the normal sequence of the program. There are two types of branch instructions: Conditional Unconditional

90. JZ addr (label). The program jumps to the instruction specified by the address (label) if the result is zero. Here the result after the execution of the preceding instruction is under consideration. JNZ addr (label). The program jumps to the instruction specified by the address (label) if the result is non-zero. JC addr (label). The program jumps to the instruction specified by the address (label) if there is a carry.

91. JNC addr (label). The program jumps to the instruction specified by the address (label) if there is no carry. JP addr (label). The program jumps to the instruction specified by the address (label) if the result is plus. JM addr (label). The program jumps to the instruction specified by the address (label) if the result is minus.

92. JPE addr (label). The program jumps to the instruction specified by the address (label) if the result contains even number of 1’s. JPO addr (label). The program jumps to the instruction specified by the address (label) if the result contains odd number of 1’s.

93. CALL addr (label). [[SP]-1] [PCH] [[SP]-2] [PCL] [SP] [SP]-2 [PC] addr (label) CALL instruction is used to call a subroutine. Before the control is transferred to the subroutine, the address of the next instruction of the main program is saved in the stack.

94. Conditional CALL addr (label) Addressing: immediate/ reg. indirect. Machine cycles:2/5. If the condition is true and program calls the specified subroutine, the execution of a conditional call instruction takes 5 machine cycle; 18 states. If condition is not true, only 2 machine cycles; 9 states are required for the execution of the instruction. i.CC addr(label) call subroutine if carry status CS=1. ii.CNC addr(label) call subroutine if carry status CS=0 iii.CZaddr(label) call subroutine if result=0; i.e zero status Z=1 iv.CNZaddr(label) call subroutine if result is not zero. Z=0 v.CPaddr(label) call subroutine if result is plus; the sign signal status S=0. vi.CMaddr(label) call subroutine if result is minus; the sign signal status S=1. vii.CPEaddr(label) call subroutine if even parity; the parity status P=1. viii.CPOaddr(label) call subroutine if odd parity; the parity status P=0.

95. RET (Return from subroutine) [PCL] <- [[SP]], [PCH] <- [[SP]+1], [SP] <- [SP] + 2. RET instruction is used at the end of a subroutine. Before the execution of a subroutine the address of the next instruction of the main program is saved in the stack. The execution of RET instruction brings back the saved address from the stack to the program counter. The content of the stack pointer is incremented by 2 to indicate the new stack top. Then the program jumps to the instruction of the main program next to CALL instruction which is called subroutine.

96. Conditional Return [PCL] <- [[SP]],[PCH]<-[[SP]+1], [SP]<-[SP] + 2. States: 6/12. Flags: none. Addressing: reg. indirect.Machine cycles:1/3.If the condition is true and the program returns from the subroutine, the execution return takes 3 m/c cycles, 12 states. If condition is not true only one m/c cycle, 6 states are required. i.RCreturn from subroutine if carry status CS=1. ii.RNCreturn from subroutine if carry status CS=0. iii.RZreturn from subroutine if result is 0; the zero status Z=1. iv.RNZreturn from subroutine if result is not 0; the zero status Z=0. v.RPreturn from subroutine if result is plus; the sign status S=1. vi.RMreturn from subroutine if result is minus; the sign status S=1. vii.RPEreturn from subroutine if even parity; the parity status P=1. viii.RPOreturn from subroutine if odd parity; the parity status P=0.

97. RST n (Restart) [[SP]-1]<- [PCH],[[SP]-2]<-[PCL] [SP]<-[SP]-2, [PC]<-8 times n. States: 12 Flags: none, Addressing: reg indirect. Machine cycles : 3 Restart is a one word call instruction starting at restart location. The address of the restart location is 8 times n. The restart instruction and location are as follows: InstructionOpcodeRestart location RST0C70000 RST1CF0008 RST2D70010 RST3DF0018 RST4 E70020

98. RST5 EF0028 RST6F70030 RST7 FF0038

99. PCHL (Jump to address specified by HL pair) [PC]<-[H-L],[PCH]<-[H],[PCL]<-[L] states 6. Addressing :register. The contents of HL pair are transferred to program counter. The contents of register H are moved to high order 8 bits of register L are transferred to low order 8 bits of register PC.

100. Stack, I/O and Machine Control Group IN port-address. (Input to accumulator from I/O port) [A]<-[Port] The data available on the port is moved to the accumulator. After instruction IN, the address of the port is specified. The 2 nd byte of instruction contains the address of the port. The address of a port is an 8-bit address.

101. OUT port-address. (O/P from accumulator to I/O port.) [Port] <-[A]. The contents of the accumulator is moved to the port specified by its address. After the OUT instruction, the port address is specified. The 2 nd byte of instruction contains the address of the port.

102. PUSH rp. (Push the content of register pair to stack) [[SP-1]<-[rh]], [[SP-2]<-[rl]], [[SP]<-[SP]-2. Contents of register pair are moved into the stack.

103. PUSH PSW (Push processor status word) [[SP]-1]<-[A], [[SP]-2]<-PSW (Program status word) [SP]<-[SP]-2. The content of the accumulator is pushed into the stack. The contents of status flag are also pushed into the stack. The content of the register SP is decremented by 2 to indicate new stacktop.

104. Interrupts in Microprocessor 8085 The primary function of the MP are: —To accept the data from input devices such as keyboard and A/D converters. —Read instructions from memory. —Process data according to the instructions. —Send results to the output devices such as LED’s printers and monitors.

105. These I/O devices are called either peripherals or I/Os. Designing logic circuits (hardware) and writing instructions (software) to enable MP to communicate with these peripherals is called interfacing and the logic circuits are called I/O ports or interfacing devices. —The microprocessor communicates with the peripherals in either or two formats. –Asynchronous means at irregular intervals. It has a low speed data transmission –Synchronous means at the same time the transmitter and receiver are synchronized with the same clock. It used for high speed data transmission

106. Interrupts in Microprocessor 8085 (cont…) The interrupt is a process of data transfer whereby an external device or a peripheral can inform the processor that it is ready for communication and it requests attention. The process is initiated by an external device and is asynchronous i.e. can be initiated at any time without reference to the system clock. The response to the interrupt is controlled by the microprocessor.

107. The interrupt request can be classified into two categories maskable and non maskable. Intel 8085 has five interrupts in the priority order : 1.TRAP 2.RST 7.5 3.RST 6.5 4.RST 5.5 5.INTR

108. Interrupts in Microprocessor 8085 (cont…) In MP 8085 the interrupt process is controlled by the Interrupt Enable flip-flop, which is internal to the processor and can be set or reset using software instructions. The working of these interrupts can be described as 1.The interrupt process is enabled by writing an instruction EI in the main program. The instruction EI sets the Interrupt Enable flip flop. The instruction DI resets the flip flop and disables the interrupt process except non maskable interrupt TRAP. 2.When the MP is executing a program, it checks the INTR line during the execution of each instruction.

109. 3.If the INTR is high and the interrupt is enabled, the MP completes the current instruction, disables the interrupt Enables flip flop and sends a signal called INTA interrupt acknowledge. The processor cannot accept any interrupt requests until the interrupt flip flop is enabled again. 4.The signal INTA is used to insert a restart (RST) instruction (or a call instruction) through external hardware. The RST instruction is a 1 byte instruction that transfers the program control to a particular location and restarts the execution at the memory location after executing step 5. 5.When the MP receives an RST instruction (or CALL instruction)

110. Interrupts in Microprocessor 8085 (cont…) Hardware and Software interrupts: Interrupts caused by I/O devices are called hardware interrupts e.g. TRAP, INTR The normal operation of the MP can also be stopped by special instruction, such instructions are called software interrupts e.g. RST n when RST n instruction is inserted in a program, the program is executed up to that point where RST n has been inserted. Interrupt call locations: When an interrupt occurs the program is transferred to a specific memory location. Then the monitor transfers the program from the specific memory location to a memory location in the memory in RAM, from where the user can write the program for interrupt sub routine. For TRAP, RST 7.5, 6.5,and 5.5 the program is automatically transferred to specific memory locations without any external hardware. The necessary hardware is already provided within 8085. An interrupt for which hardware automatically transfers the program to a specific memory location is known as vectored interrupts. The specific memory location for these interrupts are as follows.

111. InterruptCall Location TRAP0024H RST 7.5003CH RST 6.50034H RST 5.5002C

112. Interrupts in Microprocessor 8085 (cont…) INTR Call location: There are 8 number of call locations for INTR interrupt as shown in the table below: RST nCall LocationRST nCall Location RST 00000RST 40020 RST 10008RST 50028 RST 20010RST 60030 RST 30018RST 70038

113. For INTR external hardware is used to transfer program to specific CALL location. The hardware circuit generates RST codes for the purpose. The INTR line is sampled by the MP in the last state of the last machine cycle of each instruction. When INTR is high the MP saves the contents of the program counter on the stack and then sends an interrupt acknowledge signal INTA to the external hardware. In response to INTA the external hardware generates a RST n code. When MP receives this code, it transfers program to the corresponding CALL-location. Up to 8 number of I/O devices can be connected to INTR through an external hardware. Priority can be assigned to I/O devices connected to INTR through external hardware or interrupt controller. The external hardware recognizes which I/O device has interrupted and it generates proper RST code that causes microprocessor to take up ISS for that particular I/O device.