1. H.-G. Moser Max-Planck-Institut für Physik 22.06.2016 1 Future Vertex Detectors in HEP Projects: LHC (upgrade 2018+) Belle 2 (upgrade 2018+) ILC/CLIC (2020+) Requirements: High resolution (<10 µm) Low mass (<0.15% X 0 ) Fast readout (> 0.5 hits/µm²/sec) Radiation hardness (>10 MRad, > 10 15 n/cm²) Technology: Thin detectors (~ 50 µm) High granularity (pitch < 25 µm) High S/N (>20, irradiated!) Low Power (100 mW/cm² => cooling by airflow) Fast readout (<1 µs per pixel, better 25ns time stamp) Complex data processing inside pixel

2. H.-G. Moser Max-Planck-Institut für Physik Belle II, ILC, CLIC 22.06.2016 2 Belle IIILCCLIC (integr)CLIC (stamp) rate0.40.13140 hits/µm²/s 0.160.040.07 hits/mm²/BX 106.821.84 hits/mm²/train Bunch train-2670312 bunches  T bunch 43120.5 ns time∞10000.15 µs repet550 Hz frame time20500.150.025µs hits/frame8.00E-066.41E-062.10E-053.50E-06hits/µm²/s pitch50251025µm occupancy2.00%0.40%0.21%0.22% Belle II: occupancy rather high: upgrade with shorter frame time needed want a factor 10 (2-4 in sight – but not if pitch is reduced!) ILC: easy CLIC: integrated (frame) readout requires small pitch – not compatible time stamp: not compatible with frame readout

3. H.-G. Moser Max-Planck-Institut für Physik 22.06.2016 3 DEPFET FET on fully depleted silicon Baseline for Belle II PXD High granularity (resolution, occupancy) Yes High readout speed (complex processing) No: frame readout O(20 µs) Thin sensors (but keep high S/N) Yes, with good S/N Low power (0-mass cooling) Yes (because of rolling shutter) High fill factor (low mass) Yes: monolithic wafer scale sensors Add functionalities (calibration, 0-suppression, clustering) No (only in readout ASIC) Radiation hardness ok to 10 Mrad

4. H.-G. Moser Max-Planck-Institut für Physik 22.06.2016 4 State of the art: hybrid pixels Face to face interconnection: ASIC - Sensor Pitch: 50  m High granularity (resolution, occupancy) bump bonding limits pitch to O(50 µm) High readout speed (complex processing) Yes! Thin sensors (but keep high S/N) No (250 µm Sensor + ASIC + interconnect) Low power (0-mass cooling) No: liquid cooling needed High fill factor (low mass) No: 71% (ATLAS) Add functionalities (calibration, 0-suppression, clustering) ok, especially going to even smaller DSM Radiation hardness Yes (> 10 15 n/cm²)

5. H.-G. Moser Max-Planck-Institut für Physik 22.06.2016 5 CMOS Sensors Charge collection by diffusion (in un-depleted epi layer) CMOS readout electronic integrated. Small signal, yet S/N > 20) High granularity (resolution, occupancy) yes (depends on functionality/pixel) High readout speed (complex processing) yes for triple well technology Thin sensors (but keep high S/N) yes (small signal anyway) Low power (0-mass cooling) yes (depends on speed and complexity) High fill factor (low mass) needs tiling Add functionalities (calibration, 0-suppression, clustering) yes, for triple well Radiation hardness marginal (cc by diffusion) high resistivity substrates become available Performance limited by use of NMOS only: slow, no complex processing Digital section Analog section Deep N-well sensing electrode P-well N-well NMOS PMOS P-type epilayer or substrate 2D CMOS technology Trends: triple well, deep p-well => full CMOS possible (complex, fast) high resistivity epi: depletion, fast, large signal (IBM 90 nm)

6. H.-G. Moser Max-Planck-Institut für Physik 22.06.2016 6 6 Bonded wafer : High Resistivity (Sensor) + Low Resistivity (CMOS). Truly Monolithic Detector (-> High Density, Low material, Thin Device). Standard CMOS can be used (-> Complex functions in a pixel). No mechanical bonding (-> High yield, Low cost). Fully depleted sensor with small capacitance of the sense node (~10fF, High conversion gain, Low noise) Based on standard technology No Latch Up, Rad Hard. Low Power 6 SOI Sensors High granularity (resolution, occupancy) yes High readout speed (complex processing) yes Thin sensors (but keep high S/N) yes Low power (0-mass cooling) yes (depends on speed and complexity) High fill factor (low mass) needs tiling Add functionalities (calibration, 0-suppression, clustering) yes, full CMOS available Radiation hardness DSM: yes: BOX ?

7. H.-G. Moser Max-Planck-Institut für Physik 22.06.2016 7 3D Interconnection Basic Problem: How to integrate good sensors and good electronic circuits? 3D Interconnection: Two or more layers (=“tiers”) of thinned semiconductor devices interconnected to form a “monolithic” circuit.  Different layers can be made in different technology (high ohmic, BiCMOS, deep sub-  CMOS, SiGe,…..).  3D is driven by industry:  Reduces R,L and C.  Improves speed.  Reduces interconnect power, x-talk.  Reduces chip size.  Each layer can be optimized individually. Si pixel sensor BiCMOS analogue CMOS digital

8. H.-G. Moser Max-Planck-Institut für Physik CLIC09 CERN 15. Oct 09 8 HEP applications Digital section Deep N-well sensing electrode Analog section e 1 st tier Improved CMOS sensors Transfer most (if not all) of the PMOSFETs to 2nd tier (VIPIX) High CCE More functionality Or Use high resistivity CMOS as 1st tier (IPHC) Evolution of hybrid pixels  Thin devices  Smaller pitch (need good FE-ASIC!) Use DEPFET as first tier (intrinsic amplification, simpler FE-ASIC) Problem: power: all pixels on 80W/cm² => scaling: L ~ 1 µm => 1 W/cm²

9. H.-G. Moser Max-Planck-Institut für Physik 9  Alternative to bump bonding (less process steps “lower cost” (EMFT)).  Small pitch possible (~ 20  m, depending on pick & place precision).  Stacking possible (next bonding process does not affect previous bond).  Wafer to wafer and chip to wafer possible.  However: no rework possible. EMFT SLID Process FE-I3 Sensor 27  m Cu 3 Sn Cu 6 Sn 5

10. H.-G. Moser Max-Planck-Institut für Physik 10 MPP-HLL SLID module (with ALTAS FEI3)  All channels are connected and functioning  Noise value comparable to n-in-p SCMs connected by bump-bonding (~170-190 e - ) Threshold noise: 183 e-

11. H.-G. Moser Max-Planck-Institut für Physik 22.06.2016 11 Future DEPFETs Advantages: good signal to noise (at high bandwidth: 50 MHz!) large, monolithic sensors (large fill factor) low power (only 1% of pixels are on) Disadvantages: long integration time – no time resolution! needs auxiliary electronics (problem for forward detector) no data processing in pixel (only at EOS) present technology does not allow pitch below 20 µm Idea: can the DEPFET be a sensor tier in a 3D detector? (fast, with good S/N) power! DEPFET pixel dissipates 250µW with 25 x 25 µm² pitch: 40 W/cm² Can this be improved by changing design parameters?

12. H.-G. Moser Max-Planck-Institut für Physik 22.06.2016 12 Future DEPFETs g m transconductance L: gate length W: gate width  : mobility C ox : oxide sheet capacitance Id: drain current C: sensor capacitance t  shaping time (=integration time/  DEPFETCMOS CSA Gate length L~ 5 µm< 130 nm Drain current I d 50-100 µA< 10 µA Transconductance g m 40 µS>500 µS Capacitance CGate: 20 fFPixel: 100 fF Main advantage of DSM CMOS: small L, thin oxide (However, DEPFET has small C)

13. H.-G. Moser Max-Planck-Institut für Physik 22.06.2016 13 For ‘real’ detectors DEPFET 50 x 50 µm² ATLAS FEI3 50 x 400 µm² CMOS 130 nm 25 x 25 µm² L4.5 µm250 nm130 nm Id50 µA20 µA1 µA gm40 µS800 µS30 mS C20 fF400 fF100 fF Bandwidth (pixel)50 MHz40 MHz1 MHz Integration time10 µs25ns1 µs ENC40 el150 el10 el Power/pixel250 µW 32µW (analog) 76µW (total) 1 µW (analog) Power/area100mW/cm²380mW/cm²160mW (+digital) DEPFETs are competitive (or superior) in terms of noise and speed Since only a small fraction of pixels is powered at a time (1%), power consumption is very small However, the price is the long frame readout and the occupancy! Big problem at future high luminosity colliders

14. H.-G. Moser Max-Planck-Institut für Physik 22.06.2016 14 Scaled DEPFET DEPFET 25 x 25 µm² CMOS 130 nm 25 x 25 µm² L1.5 µm130 nm d ox50 nm5 nm Id1 µA3 µA gm20 µS700 µS C20 fF100 fF Bandwidth20 MHz Integration time25ns ENC38 el34 el Power/pixel5 µW Power/area0.8 W/cm² However: DCD type amplifier still needed for DEPFET Digital power in addition!

15. H.-G. Moser Max-Planck-Institut für Physik 22.06.2016 15 Summary DEPFET Present DEPFET with frame readout is an unmatched pixel sensor excellent S/N, low material, low power Readout speed at the limit (2-4x improvement possible) However, because of high power single pixel readout (with dedicated 3D integrated ASIC) seems to be excluded This could be improved using DEPFETs with smaller feature size (L) (which needs R&D and investments (technology) Still: DEPFETs would be expensive and have a long production cycle (18 months) CMOS is rather cheap, and the typical turnaround in a fab is 3 months Power becomes a problem for all technologies!

16. H.-G. Moser Max-Planck-Institut für Physik 22.06.2016 16 Future: Smart SiPMs clock x, y, t SiPM HV CMOS CMOS digital Connect ASIC chip to SIPM For each pixel: signal detection & active quenching ‘standard SIPM’ can work as tracker with SiMPL: back illumination possible (optical device) -Fast timing -Low threshold -> low gain -Active quenching -> low gain -Minimal cross-talk -Single pixel position resolution -Veto of noisy pixels Could be made using Bump bonding 3D integration techniques MIP

17. H.-G. Moser Max-Planck-Institut für Physik Features 22.06.2016 17 Dark rate: 1 MHz/mm² = 1 hit/µm²/s = O(Belle II) With 10 µm pitch and 25 ns time stamp: occupancy: 2.5 x10 -6 Power (analogue): ~ 5 µW/cm² Dominated by dark rate (even at CLIC the continuous rate is ~1kHz/mm²) R&D issues: Radiation hardness (dark rate increases due to bulk damage) Cross talk Efficiency (fill factor) Digital power

18. H.-G. Moser Max-Planck-Institut für Physik 18 Possible Problems Radiation Damage ( increas dark rate)) ~ I =   V  = 3.9x10 -17 A/cm  =10 12 n/cm ² Rate: 240 hits/µm²/s Occupancy in a 10 x 10 µm² and 25 ns time stamp: 6x10 -4 Cross talk O(10%) in 1 mm² ?? Reduce by operating at lower voltage MIP: 80 pairs/µm 10% single electron efficiency: >98% for a MIP =>Lower dark rate =>Lower cross talk Fill factor:  80% for large pixels  drift region underneath HF may help  double layer sensor?

19. H.-G. Moser Max-Planck-Institut für Physik 22.06.2016 19 Conclusions Further Development of DEPFETs radiation hardness high readout speed -> seems to be limited (frame readout) DEPFETs with smaller structure sizes for single pixel readout -> just matches performance of DSM CMOS -> Integration technology will be indispensable SiPMs + 3D integration: potential for high rate & low power tracker Integration (flip chip bump bonding, 3D) becomes key technology CMOS development increasingly important Sensor tier: reduce complexity, outsource production eventually