1. Low Mass, Radiation Hard Vertex Detectors R. Lipton, Fermilab Future experiments will require pixelated vertex detectors with radiation hardness superior to the DEPFET based devices now under construction for Belle II. 50 micron pixel size ~0.2% radiation length/layer 20  s frame time Technology development over the last ~10 years, primarily aimed at ILC, complemented by LHC and others can provide a number of possible candidate technologies with appropriate mass and power dissipation. R. Lipton Argonne IF Workshop1

2. Engineering The low capacitance associated with a small (50  m) pixel means that thin (50-100) micron sensors can be used with acceptable signal/noise. – Such detectors also can have higher fields, can be depleted more easily and have better charge collection efficiency than thick sensors if heavily irradiated Low power is crucial if air cooling is to be used – power is related to noise considerations: g m ~I d so we want to operate with as long an integration time (t s ) as practical and fairly low drain current

3. Candidate Sensor Technologies xCCDs – Not radiation hard ?CMOS Active Pixels – Moderately rad hard – Depends on technology Silicon On Insulator (SOI) – Depends on technology 3D – Rad hard ?DEPFET – Current technology – Moderately rad hard Hybrid – Rad hard – Larger pitch and mass p+ n+ rear contact drainbulksource p s y m m e t r y a x i s n+ n internal gate top gateclear n - n+ p+ - - + + + + - ~1µm 50 µm - - -- -- CCD CMOS Active Pixels SOI 3D DEPFET

4. SOI in more Detail An SOI device contains a thin (200nm) silicon transistor layer mounted on a “handle” wafer. Handle can be high resistivity detector grade silicon – First studied in 1993 by CERN/CPPM/IMEC Via through box to contact substrate KEK-organized multiproject runs with OKI/Lapidis Parallel work on thinning/backside process at FNAL/LBNL Development of laser anneal process (FNAL/Cornell) “Standard” SOI suffers from “back gate” effects where the bias on the detector affects the transistor operating point. The same effect holds for irradiation, where charge is induced in the buried oxide causing transistor shifts.

5. Solutions to the Back Gate Nested well shielding implants for SOI and CMOS devices – under active development – Reduce digital-analog coupling and backgate effects (FNAL/KEK) Thicker top silicon layers – bulk silicon acts as shield layer – TowerJazz process – vias need to be developed Dual gated transistors (FLEXFET) with bottom gate acting as a shield. SBIR funded/foundry out of business

6. 3D in more detail A three-dimensional integrated circuit is a chip with two or more layers of active electronic components, vertically integrated into a single circuit Interconnects using through silicon vias The layers (tiers) can fabricated in different optimized processes. Industry is moving toward 3D to improve circuit performance. – Reduce R, L, C for higher speed – Reduce chip I/O pads – Provide increased functionality – Reduce interconnect power and crosstalk Integrate rad hard sensors and readout electronics 1 st wafer WB/BB pad TS V Inter- tier bond pads Qualcomm 3DIC Conf

7. Interconnect Technologies (Tezzaron) (Ziptronix) (T-Micro) (RTI) Indium Oxide Cu-Cu Cu-Sn Adhesive (IZM)

8. Active Edge/3D Integration Rad-hard sensor/readout tiles 3D or vertically integrated electronics provides a backside path for extraction of signals Active edge sensors remove dead area at the edges These tiles can be used to build large area pixelated arrays with good yield and reasonable cost Need to develop sensor wafers in 200mm wafer technology Handle wafer sensor trenches Buried oxide readout IC and pads 200 micron

9. Summary Candidates for rad hard fine pitch pixelated vertex detectors: Hybrid – Available now – higher mass, pitch limited to ~50-100 microns CMOS MAPS – available now, need special processes for radiation hardness 3D – Available with some R&D. Pitch can be 20 microns SOI – Available with some R&D