1. 0 /59 Nyquist Rate ADCs Dr. Hossein Shamsi ECE Dept, K.N. Toosi University of Technology

2. 1 /59 Content  Sample & Hold Circuits  Voltage Comparators  Dual-Slope ADC  Flash and Interpolating ADCs  SAR ADC  Cyclic ADC  Two-Step ADC  Pipelined ADC  Time Interleaved ADC

3. 2 /59 Dual Slope (Integrating) ADC

4. 3 /59 Dual Slope (Integrating) ADC It is simply proven that “Bout” denotes the desired output code.

5. 4 /59 Content  Sample & Hold Circuits  Voltage Comparators  Dual-Slope ADC  Flash & Interpolating ADCs  SAR ADC  Cyclic ADC  Two-Step ADC  Pipelined ADC  Time Interleaved ADC

6. 5 /59 Flash ADC

7. 6 /59 Other Issues Comparator input current results in errors in the derived reference voltages, “resistor- string bowing”.

8. 7 /59 Interpolation

9. 8 /59 Concept

10. 9 /59 Example: Interpolating Factor of 4

11. 10 /59 Content  Sample & Hold Circuits  Voltage Comparators  Dual-Slope ADC  Flash and Interpolating ADCs  SAR ADC  Cyclic ADC  Two-Step ADC  Pipelined ADC  Time Interleaved ADC

12. 11 /59 Flow Graph for the Successive-Approximation Approach

13. 12 /59 D/A Converter-Based Successive- Approximation Converter

14. 13 /59 Another Flow Graph for the Successive-Approximation Approach

15. 14 /59 Successive Approximation Register ADC

16. 15 /59 Implementation

17. 16 /59 Sampling Phase (5-bit Example)

18. 17 /59 Bit5 Test (MSB)

19. 18 /59 Bit4 Test (Assuming bit5=0)

20. 19 /59 Speed Estimate

21. 20 /59 Limitations Conversion rate is N times smaller than the clock frequency. Conversion rate typically limited by finite bandwidth of RC network during sampling and bit-tests For high resolution, the binary weighted capacitor array can become quite large – E.g. 16-bit resolution, C total ~100pF for reasonable kT/C noise contribution If matching is an issue, an even larger value may be needed – E.g. if matching dictates C min =10fF, then 2 16 C min =655pF

22. 21 /59 High Performance Example

23. 22 /59 Low Power Example

24. 23 /59 Content  Sample & Hold Circuits  Voltage Comparators  Dual-Slope ADC  Flash and Interpolating ADCs  SAR ADC  Cyclic ADC  Two-Step ADC  Pipelined ADC  Time Interleaved ADC

25. 24 /59 Algorithmic (or Cyclic) ADC

26. 25 /59 Algorithmic (or Cyclic) ADC Signed input

27. 26 /59 Content  Sample & Hold Circuits  Voltage Comparators  Dual-Slope ADC  Flash and Interpolating ADCs  SAR ADC  Cyclic ADC  Two-Step ADC  Pipelined ADC  Time Interleaved ADC

28. 27 /59 General Concept of Multi-Step Conversion EDITTED !

29. 28 /59 Analysis EDITTED !

30. 29 /59 Input to Fine Quantizer (Vres) Aggregate=total

31. 30 /59 Alternative Illustration

32. 31 /59 Limitations EDITTED !

33. 32 /59 Input to Fine Quantizer with Gain

34. 33 /59 An 8-bit Ideal two-step ADC

35. 34 /59 An 8-bit two-step ADC with Digital Error Correction

36. 35 /59 Content  Sample & Hold Circuits  Voltage Comparators  Dual-Slope ADC  Flash and Interpolating ADCs  SAR ADC  Cyclic ADC  Two-Step ADC  Pipelined ADC  Time Interleaved ADC

37. 36 /59 Pipeline ADC Block Diagram

38. 37 /59 Pipeline ADC Characteristics

39. 38 /59 Stage Analysis

40. 39 /59 Stage Model with Ideal DAC

41. 40 /59 "Residue Plot" (2-bit Sub-ADC)

42. 41 /59 Upper Bound for Stage Gain Example: First stage with 2-bit sub-ADC, followed by 2-bit backend ADC D out =D+G -1 D b

43. 42 /59 2 Different Explanation 00XX XX00 00XX XX00 XX00 00XX D: :D Output bits extraction algorithms: Both have the same result! + Output code : + : Output code EDITTED(ADDED) !

44. 43 /59 Issue with G=2 B

45. 44 /59 Idea #1: G slightly less than 2 B

46. 45 /59 Idea #2: G =2 B-1

47. 46 /59 Idea #3: G=2 B, Extended Backend Range

48. 47 /59 Variant of Idea #2: "1.5-bit stage“ G =2 B-1

49. 48 /59 1.5-bit Gain Stage

50. 49 /59 1.5-bit Gain Stage non-idealities

51. 50 /59 Block diagram of a 12-bit pipelined ADC Pipelined ADC with four 3-bit stages (each stage resolves two bits).

52. 51 /59 Block diagram of a B×N-bit pipelined ADC

53. 52 /59 AD9042

54. 53 /59 Sampled data n-bit residue generator (N = 2 n )

55. 54 /59 Pipelined ADC (composed of 2-bit gain-stages)

56. 55 /59 Pipelined ADC (composed of 1.5-bit gain-stages)

57. 56 /59 1.5-Bit Stage Implementation

58. 57 /59 Residue Plot

59. 58 /59 Content  Sample & Hold Circuits  Voltage Comparators  Dual-Slope ADC  Flash and Interpolating ADCs  SAR ADC  Cyclic ADC  Two-Step ADC  Pipelined ADC  Time Interleaved ADC

60. 59 /59 Time-Interleaved ADC